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Appendix B
Timing Diagrams
B-22
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•
Sample Clock Timebase
—This signal can be used to generate the
Sample Clock. This signal acts as the clock for the UI counter, and a
Sample Clock can be generated every N periods of the Sample Clock
Timebase by programming the UI counter accordingly. This signal can
come from an internal source (such as the board oscillator) or an
external source.
•
Sync Sample Clock Timebase
—The Sync Sample Clock Timebase is
a signal that is generated internally and is related to the Sample Clock
Timebase. How it is generated and the relationship between the two
signals depends on the mode of operation. In general, the Sync Sample
Clock Timebase is used to synchronize the input signals to the analog
output timing engine before they are used by the Sample Clock
Timebase.
•
Start Trigger, Selected Start
—The Start Trigger determines when a
timed analog output operation will start. This signal can come from a
software command or an external pulse. Selected Start is the output of
the selection block for the Start Trigger source.
•
Pause Trigger, Selected Pause
—The waveform generation can be
paused using the pause trigger. When enabled, the waveform
generation will occur as long as the gate is enabled. The generation
will be paused if the gate is disabled. This signal can come from a
software command or an external signal. The Selected Pause is the
output of the selection block for the Pause Trigger source.
•
Start_Trig, RTSI, or PFI
—These terminals are the I/O interface for
the device. All external triggers are input on these terminals. Internal
signals can be exported to these terminals as well.
•
_i Signals
—All signals marked with _i are external signals that have
been through the I/O buffers and are ready for internal use.
Input Timing
Input timing
refers to the delays of importing signals from the external
terminals so that the analog output timing engine can use them as sources
for different triggers or clocks. Figure B-23 and Table B-12 describe the
insertion delays for external signals.