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Appendix B
Timing Diagrams
B-8
ni.com
Convert Clock
Convert Clock is the signal that determines when an analog to digital
conversion is started. The signal going to the ADC is called p_AI_Convert.
Convert Clock also can be routed to several external I/O terminals for
external use. Convert Clock is always generated from the Convert Clock
Timebase signal, either directly or indirectly (by dividing it down using the
SI2 counter). If the SI2 counter is used, it is assumed that a reliable
free-running clock is being used. Refer to the
section for
the timing relationship between Convert Clock Timebase and Sync Convert
Clock Timebase. If the SI2 counter is not being used (external convert
case), the Convert Clock Timebase is assumed to be not free-running and
the relationship between the Convert Clock Timebase and the Sync Convert
Clock Timebase is an asynchronous delay.
Whether the SI2 counter is used or not, the timing parameters in the
generation of Convert Clock are the same starting at the Convert Clock
Timebase signal.
Figure B-6.
Convert Clock and the Analog Input Timing Engine
S
t
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rt
Termin
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elected Reference Trigger
Reference Trigger
Termin
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Termin
a
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elected
Sa
mple Clock
Termin
a
l
Termin
a
l
Termin
a
l
S
elected
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t
a
rt
RT
S
I
Termin
a
l
Termin
a
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Termin
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l
S
elected P
aus
e Trigger
S
I
Co
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nter
Block
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I2
Co
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nter
Block
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I_TC
Sa
mple Clock Time
bas
e
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ync
Sa
mple Clock Time
bas
e
Convert Clock Time
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ync Convert Clock Time
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I
S
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rt
P
aus
e Trigger
p_AI_Convert
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a
rt
1
S
I2_TC