Chapter 3
Hardware Overview
3-12
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Programmable Function Inputs
The 10 PFIs are connected to the signal routing multiplexer for each timing
signal, and software can select one of the PFIs as the external source for a
given timing signal. It is important to note that any PFI can be used as an
input by any timing signal and that multiple timing signals can
simultaneously use the same PFI. This flexible routing scheme reduces the
need to change physical connections to the I/O connector for different
applications. You also can individually enable each PFI pin to output a
specific internal timing signal. For example, if you need the UPDATE*
signal as an output on the I/O connector, software can enable the output
driver for the PFI5/UPDATE* pin.
Device and RTSI Clocks
Many functions performed by the NI 6115/6120 require a frequency
timebase to generate the necessary timing signals for controlling A/D
conversions, updates, or general-purpose signals at the I/O connector.
The NI 6115/6120 can use either its internal 20 MHz timebase or a
timebase received over the RTSI bus. In addition, if you configure the
device to use the internal timebase, you can also program the device to drive
its internal timebase over the RTSI bus to another device that is
programmed to receive this timebase signal. This clock source, whether
local or from the RTSI bus, is used directly by the device as the primary
frequency source. The default configuration at startup is to use the internal
timebase without driving the RTSI bus timebase signal. This timebase is
software selectable.
RTSI Triggers
The seven RTSI trigger lines on the RTSI bus provide a very flexible
interconnection scheme for any device sharing the RTSI bus. These
bidirectional lines can drive any of eight timing signals onto the RTSI bus
and can receive any of these timing signals. The RTSI trigger lines connect
to other devices through the PXI bus on the PXI backplane or through a
special ribbon cable that must be installed for PCI. Figure 3-12 shows the
PCI signal connection scheme and Figure 3-13 shows the PXI connection
scheme.