Chapter 1
Introduction
1-2
ni.com
you do not need the RTSI cable for system triggering and timing on the
PXI. In addition, a phase-locked loop (PLL) circuit accomplishes the
synchronization of multiple NI PXI-6115/6120 devices or other PXI
devices which support PLL synchronization by allowing these devices to
all lock to the same reference clock present on the PXI backplane. Refer to
the
,
for more information.
Detailed specifications of the NI 6115/6120 are in Appendix A,
Using PXI with CompactPCI
The ability to use PXI-compatible products with standard CompactPCI
products is an important feature of
PXI Specification Revision 2.0
. If you
use a PXI-compatible plug-in device in a standard CompactPCI chassis,
you are unable to use PXI-specific functions, but you can still use the basic
plug-in device functions. For example, the RTSI interface on the
NI PXI-6115/6120 is available in a PXI chassis, but not in a CompactPCI
chassis.
The CompactPCI specification permits vendors to develop sub-buses that
coexist with the basic PCI interface on the CompactPCI bus. Compatible
operation is not guaranteed between CompactPCI devices with different
sub-buses nor between CompactPCI devices with sub-buses and PXI
devices. The standard implementation for CompactPCI does not include
these sub-buses. The NI PXI-6115/6120 works in any standard
CompactPCI chassis adhering to PICMG CompactPCI 2.0 R3.0.
PXI-specific features are implemented on the J2 connector of the
CompactPCI bus. Table 1-1 lists the J2 pins used by the NI PXI-6115/6120.
The PXI device is compatible with any CompactPCI chassis with a sub-bus
that does not drive these lines. Even if the sub-bus is capable of driving
these lines, the PXI device is still compatible as long as those pins on the
sub-bus are disabled by default and are never enabled.
Caution
Damage can result if these lines are driven by the sub-bus.