Index
©
National Instruments Corporation
I-7
PFI9/GPCTR0_GATE signal
See also
GPCTR0_GATE signal
description (table), 4-5
signal summary (table), 4-7
PFIs (programmable function inputs)
questions about, B-5
signal name equivalencies (table), B-5
signal routing, 3-10
timing connections, 4-20
phase-locked loop circuit
block diagram, 3-10
description, 3-9
phone technical support, C-2
physical specifications, A-17
pin assignments
I/O connector (figure), 4-2
PXI-6115/6120 J2 pin assignments
PLL.
See
phase-locked loop circuit
polarity.
See
input polarity and range
posttriggered data acquisition, 4-20
power connections
+5 V power pins, 4-18, B-2
incorrect connections (caution), 4-18
power-on states of PFI and DIO lines, B-6
self-resetting fuse, 4-18, B-2
power requirement specifications, A-17
power-on states of PFI and DIO lines, B-6
pretriggered data acquisition, 4-21
professional services, C-1
programmable function inputs (PFIs).
PFIs (programmable function inputs)
programming examples, C-1
pseudodifferential signal connections
definition, 4-8
ground-referenced signals (figure), 4-9
PXI
PXI-6115/6120 J2 pin assignments
Q
questions and answers
analog input and output, B-3
general information, B-1
installation and configuration, B-2
timing and digital I/O, B-5
R
Real-Time System Integration.
See
RTSI
requirements for getting started, 1-3
RTSI
bus signal connections (figure), 3-13
clocks
correlating DIO signals, 4-16
description, 3-12
overview, 1-1
triggers
description, 3-12
specifications, A-17
S
safety information, 1-8
safety specifications, A-18
sampling rate
scan counter
typical posttriggered acquisition
typical pretriggered acquisition, 4-21
SCANCLK signal
description (table), 4-3
signal summary (table), 4-6
timing connections, 4-28