Chapter 3
Hardware Overview
3-4
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High-Speed Timing
The high-speed timing circuitry on the PCI-1424, built from high-speed
counters, allows you to specify or generate precise, real-time control
signals. You can map the output of this circuitry to a trigger line to provide
accurate pulses and pulse trains.
Acquisition and ROI
The acquisition and region-of-interest (ROI) circuitry monitors the
incoming video signals and routes the active
to the multiple-tap data
formatter and SDRAM memory. In an ROI acquisition, you select an area
within the
to transfer to the PCI bus.
Scatter-Gather DMA Controllers
The PCI-1424 uses three independent onboard direct memory access
(DMA) controllers. The DMA controllers transfer data between the
onboard SDRAM memory buffers and the PCI bus. Each of these
controllers supports
, which allows the DMA
controller to reconfigure on-the-fly. Thus, the PCI-1424 can perform
continuous image transfers directly to either contiguous or fragmented
memory buffers.
Device Configuration NVRAM
The PCI-1424 contains onboard nonvolatile RAM (
) that
configures all registers on power-up.
Start Conditions
The PCI-1424 can start acquisitions in a variety of conditions:
•
Software control—The PCI-1424 supports software control of
acquisition start. You can configure the PCI-1424 to capture a
fixed number of
or
. This configuration is useful for
capturing a single frame or a sequence of frames.
•
Trigger control—You can start an acquisition by enabling external
or RTSI bus trigger lines. Each of these inputs can start a video
acquisition on a rising or falling edge.
