Chapter 3
Signal Connections
©
National Instruments Corporation
3-25
generate the gate signal in this application. If you use a second counter,
however, you must externally invert the signal.
Figure 3-15.
Frequency Measurement Application
The GATE, CLK, and OUT signals for counters B1 and B2 are available at
the I/O connector. The GATE and CLK pins are internally pulled up to +5 V
through a 100 k
Ω
resistor. Refer to Appendix A,
, for signal
voltage and current specifications.
The following specifications and ratings apply to the 82C53 I/O signals:
•
Absolute max
–0.5 to +5.5 V
voltage input rating
with respect to DGND
•
82C53 digital input specifications (referenced to DGND):
–
V
ih
input logic high voltage
2.2 V min
5.3 V max
–
V
il
input logic low voltage
–0.3 V min
0.8 V max
–
Input load current
–10
µ
A min
+10
µ
A max
+5 V
I/O Connector
CLK
GATE
OUT
DGND
PCI-1200
Gate
Source
Signal
Source
Counter
100 k
Ω
13
