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4-3
DI Sample Clock Signal
Use the DI Sample Clock (di/SampleClock) signal to sample digital I/O on any slot using
parallel digital modules, and store the result in the DI waveform acquisition FIFO. If the cDAQ
controller receives a DI Sample Clock signal when the FIFO is full, it reports an overflow error
to the host software.
A sample consists of one reading from each channel in the DI task. DI Sample Clock signals the
start of a sample of all digital input channels in the task. DI Sample Clock can be generated from
external or internal sources as shown in Figure 4-1.
Figure 4-1.
DI Sample Clock Timing Options
Routing DI Sample Clock to an Output Terminal
You can route DI Sample Clock to any output PFI terminal.
DI Sample Clock Timebase Signal
The DI Sample Clock Timebase (di/SampleClockTimebase) signal is divided down to provide
a source for DI Sample Clock. DI Sample Clock Timebase can be generated from external or
internal sources. DI Sample Clock Timebase is not available as an output from the controller.
Using an Internal Source
To use DI Sample Clock with an internal source, specify the signal source and the polarity of the
signal. Use the following signals as the source:
•
AI Sample Clock
•
AO Sample Clock
•
Counter
n
Internal Output
•
Frequency Output
•
DI Change Detection Output
Several other internal signals can be routed to DI Sample Clock. Refer to the
Device Routing in
MAX
topic in the
NI-DAQmx Help
or the
LabVIEW Help
for more information.
Programmable
Clock
Divider
DI Sample Clock
Timebase
PFI
Analog Comparison Event
Ctr
n Internal Output
DI Sample Clock
Sigma-Delta Module Internal Output
Analog Comparison
Event
20 MHz Timebase
80 MHz Timebase
PFI
100 kHz Timebase
