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Chapter 3
Register Map and Descriptions — Configuration Memory Low Register
©
National Instruments Corporation
3-11
9
DitherEn
Dither Enable—This bit controls the dither circuitry
feeding the analog input. If this bit is set, approximately
±0.5 LSB of white Gaussian noise is added to the input
signal. This bit is reserved on the AT-MIO-16XE-50,
AT-MIO-16XE-10, and AT-AI-16XE-10, and should be
set to 1. Dither cannot be disabled on the
AT-MIO-16XE-50, AT-MIO-16XE-10, and
AT-AI-16XE-10.
8
Unip/Bip
Channel Unipolar/Bipolar—This bit configures the ADC
for unipolar or bipolar mode. When Unip/Bip is set, the
ADC is configured for unipolar operation and values read
from the ADC Data Register are in straight binary format.
When Unip/Bip is clear, the ADC is configured for bipolar
operation and values. The data values are two’s
complement and automatically sign extended.
2-0
Gain<2..0>
Channel Gain Select 2 through 0—These three bits control
the gain settings of the input PGIA for the selected analog
channel. The following gains can be selected on the
AT E Series:
Table 3-3. PGIA Gain Selection
Gain<2..0>
Actual Gain
000
0.5
1,2
001
1
010
2
011
5
1
100
10
101
20
1
110
50
1
111
100
1
Not supported on the AT-MIO-16XE-50.
2
Not supported on the AT-MIO-16XE-10 and AT-AI-16XE-10.
Содержание AT-MIO E Series
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