National Instruments AT-MIO-64F-5, Руководство пользователя

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Chapter 3 Theory of Operation
© National Instruments Corporation 3-21 AT-MIO-64F-5 User Manual
The Am9513A contains five independent 16-bit counter/timers, a 4-bit frequency output channel,
and five internally generated timebases. The five counter/timers can be programmed to operate
in several useful timing modes. The programming and operation of the Am9513A are presented
in detail in Appendix E, AMD Am9513A Data Sheet.
The Am9513A clock input is one-tenth the BRDCLK frequency selected by the W1 and W2
jumpers. The factory default for BRDCLK is 10 MHz, which generates a 1 MHz clock input to
the Am9513A. The Am9513A uses this clock input plus a BRDCLK divided-by-two input at
Source 2 to generate six internal timebases. These timebases can be used as clocks by the
counter/timers and by the frequency output channel. When BRDCLK is 10 MHz, the six internal
timebases normally used for AT-MIO-64F-5 timing functions are 5 MHz, 1 MHz, 100 kHz,
10 kHz, 1 kHz, and 100 Hz. The 16-bit counters in the Am9513A can be diagrammed as shown
in Figure 3-18.
SOURCE
GATE
OUT
COUNTER
Figure 3-18. Counter Block Diagram
Each counter has a SOURCE input pin, a GATE input pin, and an output pin labeled OUT. The
Am9513A counters are numbered 1 through 5, and their GATE, SOURCE, and OUT pins are
labeled GATE N, SOURCE N, and OUT N, where N is the counter number.
For counting operations, the counters can be programmed to use any of the five internal
timebases, any of the five GATE and five SOURCE inputs to the Am9513A, and the output of
the previous counter (Counter 4 uses Counter 3 output, and so on). A counter can be configured
to count either falling or rising edges of the selected input.
The counter GATE input allows counter operation to be gated. Once a counter is configured for
an operation through software, a signal at the GATE input can be used to start and stop counter
operation. The five gating modes available with the Am9513A are as follows:
• No gating
• Level gating active high
• Level gating active low
• Low-to-high edge gating
• High-to-low edge gating