National Instruments AT-MIO-64F-5, Руководство пользователя

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Theory of Operation Chapter 3
AT-MIO-64F-5 User Manual 3-12 © National Instruments Corporation
Interval Scanning Data Acquisition Timing
Interval scanning assigns a time between the beginning of consecutive scan sequences. If only
one scan sequence is in the configuration memory list, the circuitry stops at the end of the list
and waits the necessary interval time before starting the scan sequence again. If multiple scan
sequences are in the configuration memory list, the circuitry stops at the end of each scan
sequence and waits the necessary time interval before starting the next scan sequence. When the
end of the scan list is reached, the circuitry stops and waits the necessary time interval before
sequencing through the channel information list again. Figure 3-8 shows an example of the
interval scanning sequence timing.
Trigger*
DAQPROG
DAQCMPLT
DAQCLEAR*
Interrupt
Channel
SCANCLK
COUNTER2
CONVERT
0 1 0 1 0
Figure 3-8. Interval Scanning Posttrigger Data Acquisition Timing
In interval-scanning applications, the first sample does not occur until after the first falling edge
of the Counter 2 output, or one scan interval after the trigger. Scanning stops at the end of the
first scan sequence or at the end of the entire scan list. The sequence restarts after a rising edge
on Counter 2 is detected. The interval-scanning mode is useful for applications where a number
of channels need to be monitored over a long period of time. Interval-scanning monitors the
N
channels every scan interval, so the effective channel conversion interval is equal to the interval
between scans.
Data Acquisition Rates
The acquisition and channel selection hardware function so that in the channel scanning mode,
the next channel in the channel configuration register is selected immediately after the
conversion process has begun on the previous channel. With this method, the input multiplexers
and the PGIA begin to settle to the new value while the conversion of the last value is still taking
place. The circuitry on the AT-MIO-64F-5 is designed and defined to settle to within 0.5 LSBs,
or 0.01% of full scale, in 5 µsec.
Analog Output and Timing Circuitry
The AT-MIO-64F-5 has two channels of 12-bit D/A output. Unipolar or bipolar output and
internal or external reference voltage selection are available with each analog output channel
through a register in the AT-MIO-64F-5 register set. Figure 3-9 shows a block diagram of the
analog output circuitry.