National Instruments AT-MIO-64F-5, Руководство пользователя

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Chapter 3 Theory of Operation
© National Instruments Corporation 3-9 AT-MIO-64F-5 User Manual
interval timing signals. The sample-interval timer can also use any of the external clock inputs
to the Am9513A as a timebase. During data acquisition, the sample interval counts down at the
rate given by the internal timebase or external clock. Each time the sample-interval timer
reaches zero, it generates an active low pulse and reloads with the programmed sample-interval
count, initiating a conversion. This operation continues until data acquisition halts.
External control of the sample interval is possible by applying a stream of pulses at the
EXTCONV* input. In this case, you have complete external control over the sample interval
and the number of A/D conversions performed. All data acquisition operations are functional
with external signals to control conversions. This means that in a data acquisition sequence that
employs external conversion timing, conversions are inhibited by the hardware until a trigger
condition is received, then the programmed number of conversions occurs, and conversions are
inhibited after the sequence completes. When using internal timing, the EXTCONV* signal at
the I/O connector must be left unconnected or in the high-impedance state.
Data acquisition can be controlled by the onboard sample counter. This counter is loaded with
the number of posttrigger samples to be taken during a data acquisition operation. The sample
counter can be 16-bit for counts up to 65,535 or 32-bit for counts up to 2
32 - 1. If a 16-bit
counter is needed, Counter 4 of the Am9513A Counter/Timer is used. If more than 16-bits are
needed, Counter 4 is concatenated with Counter 5 of the Am9513A to form a 32-bit counter.
The sample counter decrements its count each time the sample-interval counter generates an A/D
conversion pulse, and the sample counter stops the data acquisition process when it counts down
to zero. The sample counter can also be used to count conversions generated by external
conversion signals.
The configuration memory register is set up to select the analog input channel and configuration
before data acquisition is initiated for a single-channel data acquisition sequence. These settings
remain constant during the entire data acquisition process; therefore, all A/D conversions are
performed on a single channel. Single-channel acquisition is enabled through a register in the
AT-MIO-64F-5 register set. The data acquisition process can be initiated via software or by
applying an active low pulse to the EXTTRIG* input on the AT-MIO-64F-5 I/O connector.
Figure 3-5 shows the timing of a typical single-channel data acquisition sequence.
Trigger*
DAQPROG
DAQCMPLT
DAQCLEAR*
Interrupt
CONVERT
9 8
Sample CTR
7 6 5 4 3 2 1 10 9
Figure 3-5. Single-Channel Posttrigger Data Acquisition Timing
In this sequence, the sample-interval counter, Counter 3, is programmed to generate conversion
signals only under a certain gating signal, such as the DAQPROG signal. In addition, the sample
counter, Counter 4, is programmed to count the number of conversions generated. In this case,
the sample counter is programmed to count 10 samples, then stop the acquisition sequence.