National Instruments AT-MIO-64F-5, Руководство пользователя

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Chapter 5 Programming
© National Instruments Corporation 5-31 AT-MIO-64F-5 User Manual
Once steps 1 through 3 are completed, the DMA controller is programmed to acknowledge
requests. If analog input DMA is programmed, the DMA controller automatically reads the
ADC FIFO Register whenever an A/D conversion result is available and then stores the result in
a buffer in memory. If the DMA controller has been programmed for analog output updating,
values from the buffer in memory are automatically written to the DAC upon receipt of a DMA
request. If both analog input and output DMA is selected, then the DMA controller reads the
FIFO or writes to the DACs depending on which channel requested a DMA transfer.
If single-channel interleaved DMA is selected for writing data to the DACs, then one buffer
services both DAC 0 and DAC 1. This is accomplished by interleaving the data in the buffer.
The first location in the buffer should hold the first value to be transferred to DAC 0, the second
should hold the first value to be transferred to DAC 1, the third should hold the second value to
be transferred to DAC 0, and so on.
If dual-channel DMA operation has been selected for DMA requesting service, DMA channel A
and memory buffer A (DMA A) are served first. When a DMA terminal count is received, the
board automatically switches the DMA operation to DMA channel B and memory buffer B
(DMA B). Therefore, the board can collect data to or from one buffer and simultaneously
service data in another buffer. If the DMA controller is programmed for auto-reinitialize mode,
DMA A and DMA B are continuously served in turn.
If dual-channel DMA operation has been selected to service both analog outputs, memory buffer
A (DMA channel A) and memory buffer B (DMA channel B) are concurrently serviced, with
buffer A serving DAC 0 and buffer B serving DAC 1.
Interrupt Programming
Seven different interrupts are generated by the AT-MIO-64F-5 board:
¥ Whenever a conversion is available to be read from the ADC FIFO
¥ Whenever the ADC FIFO is more than half-full
¥ Whenever a data acquisition sequence completes
¥ Whenever a DMA terminal count is received
¥ Whenever a falling edge on the TMRTRIG* pin of the Am9513A is detected
¥ Whenever the DAC FIFO is less than full
¥ Whenever the DAC FIFO is half-full
These interrupts can be enabled either individually or in any combination. In any of the interrupt
modes, it is a good practice to confirm the source of the interrupt through reading Status
Register 1. If ADC FIFOEF* or ADC FIFOHF* is true, a conversion interrupt has occurred.
Reading from the ADC FIFO Register clears these interrupt conditions. Writing to the DAQ
Clear Register also clears these conversion interrupts. If DAQCOMP is set, the interrupt results
from the completion of a data acquisition operation. This interrupt is cleared by writing to the
DAQ Clear Register. If TMRREQ is set, a DAC update interrupt has occurred. Writing to the
TMRREQ Clear Register clears this interrupt condition. In the case that waveform generation is
disabled in Command Register 2, the DACs are not updated and the TMRREQ signal can be
used as a timer interrupt. If DMATCA or DMATCB is set, a DMATC INT has occurred on
either DMA channel A or B. Writing to the DMATCA or DMATCB Clear Register clears this
interrupt condition.