National Instruments AT-MIO-64F-5, Руководство пользователя

Страница: 149 / 266

Chapter 5 Programming
© National Instruments Corporation 5-5 AT-MIO-64F-5 User Manual
Generating a Single Conversion
An A/D conversion can be initiated in one of two waysÐa software-generated pulse or a
hardware pulse. To initiate a single A/D conversion through software, access the Single
Conversion Register. To initiate a single A/D conversion through hardware, apply an active low
pulse to the EXTCONV* pin on the AT-MIO-64F-5 I/O connector. See the
Data Acquisition
and Analog Output Timing Connections section in Chapter 2, Configuration and Installation , for
EXTCONV* signal specifications. After an A/D conversion is initiated, the ADC automatically
stores the result in the ADC FIFO at the end of its conversion cycle.
Reading a Single Conversion Result
A/D conversion results are available when ADCFIFOEF* is set in the Status Register and can be
obtained by reading the ADC FIFO Register.
To read the A/D conversion result, use the following steps:
1. Read the Status Register (16-bit read).
2. If the OVERRUN or OVERFLOW bits are set, an error occurred and data was lost.
3. If the ADCFIFOEF* bit is set, read the ADC FIFO Register to obtain the result.
Reading the ADC FIFO Register removes the A/D conversion result from the ADC FIFO and
clears the ADCFIFOEF* bit if no more values remain in the FIFO.
The ADCFIFOEF* bit indicates whether one or more A/D conversion results are stored in the
ADC FIFO. If the ADCFIFOEF* bit is not set, the ADC FIFO is empty and reading the ADC
FIFO Register returns meaningless data. After an A/D conversion is initiated, the ADCFIFOEF*
bit is set approximately 10 µsec after initiating the conversion, indicating that the data
conversion result can be read from the FIFO.
An ADC FIFO overflow condition occurs if more than 512 conversions are initiated and stored
in the ADC FIFO before the ADC FIFO Register is read. If this condition occurs, the
OVERFLOW bit is set in the Status Register to alert you that one or more A/D conversion
results have been lost because of FIFO overflow. Strobing the DAQ Clear Register resets this
error flag.
An ADC overrun condition occurs if an attempt is made to start a new conversion while the
previous conversion is being completed. If this condition occurs, the OVERRUN bit is set in
Status Register 1 to indicate an error condition or that an invalid operation occurred. Strobing
the DAQ Clear Register resets this error flag.
Programming a Single-Channel Data Acquisition Sequence
The following programming sequence for sample counts less than 65,537 leaves the data
acquisition circuitry in a retriggerable state. The sample-interval and sample counters are
reloaded at the end of the data acquisition to prepare for another data acquisition operation. The
counters do not need reprogramming, and the next data acquisition operation starts when another
trigger condition is received.