Register Descriptions
Chapter 4
SCXI-1100 User Manual
4-8
© National Instruments Corporation
Hardscan Control Register (HSCR)
The HSCR contains eight bits that control the setup and operation of the hardscan timing
circuitry of Slot 0. To write to the HSCR, follow the procedure given in the Register Writes
section in Chapter 5, Programming, using 13 as the slot number and writing eight bits to the
HSCR. The register shifts in the data present on the MOSI line, bit 7 first, when the Slot-Select
Register selects Slot 13.
Type:
Write-only
Word Size:
8-bit
Bit Map:
7
6
5
4
3
2
1
0
RSVD
FRT
RD
ONCE
HSRS*
LOAD*
SCANCONEN
CLKEN
Bit
Name
Description
7
RSVD
Reserved.
6
FRT
Forced Retransmit – When cleared to 0, causes the scan list
in the FIFO to be reinitialized to the first entry, allowing
the scan list to be reprogrammed in two steps instead of
having to rewrite the entire list. When this bit is set to 1, it
has no effect.
5
RD
Read – When cleared to 0, prevents the FIFO from being
read. When set to 1, the FIFO is read except at the end of a
scan list entry during scanning, when reading is briefly
disabled to advance to the next scan list entry.
4
ONCE
Once – When set to 1, causes the hardscan circuitry to shut
down at the end of the scan list circuitry during a data
acquisition. When cleared to 0, the circuitry wraps around
and continues seamlessly with the first scan list entry after
the entry is finished.
3
HSRS*
Hardscan Reset – When cleared to 0, causes all the
hardware scanning circuitry, including the FIFO, to be reset
to the power-on state. When set to 1, this bit has no effect.
2
LOAD*
Load – When cleared to 0, forces the Slot 0 sample counter
to be loaded with the output of the FIFO. When set to 1,
this bit has no effect.
1
SCANCONEN
Scan Control Enable – When set to 1, enables the
SCANCON lines. When cleared to 0, all SCANCON lines
are disabled (high).
0
CLKEN
Clock Enable – When set to 1, enables TRIG0 as a clock
for the hardscan circuitry. When cleared to 0, TRIG0 is
disabled.
