Chapter 2
Configuration and Installation
© National Instruments Corporation
2-25
SCXI-1162 User Manual
Figure 2-11 illustrates a read of the SCXI-1162 Data Register.
SS*
SERCLK
SERDATOUT
Tdelay
SLOT0SEL*
DAQD*/A
1
0
1 1 0 0
0 0
0 0 0 0 0 0
0 0 0
1
0
0
1
1
1
1 1
1
1
1
1
1 1
1
In (31)
In (0)
Tclk_wait DAQ*/A low to first falling edge of SERCLK 150 nsec min
Tdelay DAQ*/A high to SERDATOUT high 650 nsec max
Tclk wait
Figure 2-11. SCXI-1162 Data Register Read Timing Diagram
For further details on these registers and their addresses, refer to Chapter 4, Register
Descriptions, and Chapter 5, Programming.
