Section Six
Theory of Operation
© National Instruments Corporation
6-3
GPIB-1014P User Manual
Clock and Reset Circuitry
An LS240 receives the 16 MHz utility SYSCLK provided on the VMEbus. The Read/Write State
Machine uses the 16 MHz clock to control the timing of the signal DTACK* and the TLC inputs
RD* and WR* (see Timing Control Logic). This clock is divided to 8 MHz for the CLOCK signal
used by the TLC. The VMEbus signal SYSRESET* initializes the TLC, the interrupter, and the
timing control circuitry.
Timing Control Logic
When the GPIB-1014P is addressed (see Address Decoding in this section), AS-25 clocks the local
signal MCYC true. If another module is asserting DTACK* when MCYC becomes true (that is,
the address is pipelined to the GPIB-1014P), the GPIB-1014P waits for DTACK* to be released
and for DS0* to be asserted. The GPIB-1014P then asserts STRT after delaying a minimum of 85
nsec in order to meet the TLC address set-up time.
If DS0* is never asserted, the cycle is an Address-Only (ADO) cycle. In this case, MCYC is
cleared when AS* goes high, and the GPIB-1014P takes no further action. For more information
on ADO cycles, see IEEE Standard for a Versatile Backplane Bus: VMEbus.
An LS74A D-type flip-flop and an LS393 dual 4-bit counter implement a state machine to control
the timing during Read/Write cycles. The timing control begins when STRT becomes true. If the
VMEbus signal WRITE* is false, indicating a read cycle, the TLC RD* signal is driven true and the
data bus drivers are enabled immediately. The state machine then uses the VMEbus utility
SYSCLK to count a minimum delay of 250 nsec, which corresponds to the read access time of the
TLC. At this time, the local signal LDTACK* becomes true, signaling the DTACK* assert/release
circuitry to drive the VMEbus signal DTACK* low. This indicates that valid data is present on the
data bus. The data remains valid until DS0* is released, at which time the signals DEN* and
LDTACK* go high. The DTACK* assert/release circuitry releases DTACK* once it sees that the
bus driver has been released (DEN* is high) and that DS1 is high. The state machine then delays
for a recovery time of 250 nsec.
The timing control for a write operation is similar to a read operation. When STRT and the
VMEbus signal WRITE* are true, the TLC WR* is driven true, and the data bus receivers are
enabled immediately. The state machine counts a data setup time of 250 nsec before driving the
WR* signal false and asserting LDTACK* (thus asserting DTACK*). Data is latched into the TLC
on the trailing edge of the WR* signal. The DTACK* signal remains asserted until the bus master
releases DS0* and DS1* and the F245 releases the VME data bus. After a recovery time of 250
nsec, the state machine is ready to begin the next operation. Accesses to the GPIB-1014P during
this recovery time are recognized, but are delayed until the recovery time has elapsed.
Interrupter Logic
The interrupter circuitry permits the GPIB-1014P to request service. The circuitry consists of four
flip-flops, an F85 4-bit magnitude comparator, three 25 nsec digital delay gates, and some
miscellaneous gates.
