Section Six
Theory of Operation
© National Instruments Corporation
6-5
GPIB-1014P User Manual
The TLC is enabled during the TLC CS* pulse, and the IEEE-1014 bus address signals A1 through
A3 are decoded internally to access the appropriate register. Data on the IEEE-1014 bus are strobed
into write-only registers at the trailing edge of WR*. Data in the read-only registers are placed on
the IEEE-1014 bus in a minimum access time after TLC CS* and RD* are both true.
Most of the TLC GPIB interface functions can be implemented or activated from either side; that is,
the TLC can be programmed to do these functions by the VMEbus master or it can be addressed to
do them by the GPIB Controller. In terms of the IEEE-488 standard, the distinction between these
two modes of operation is generally the same as that between local and remote interface messages,
respectively.
The ADSR is the primary register for monitoring the current status of the TLC; that is, to determine
if it is a GPIB Talker, GPIB Listener, GPIB Active Controller, or in GPIB remote or local mode.
The CPTR provides a means to read the GPIB data bus directly and is used to recognize interface
messages that are not automatically decoded and implemented by the TLC.
The Address Register (ADR) is used to program two address registers, ADR0 and ADR1, which
contain the GPIB addresses (recognized by the TLC) and Talker and Listener disabling bits. The
manner in which the TLC uses these registers depends on the address mode established in the
ADMR. A bit in ADR1 indicates if END was set on the last byte received.
IMR1 and IMR2 are interrupt mask registers for enabling and disabling the interrupt from the TLC
on the occurrence of 13 specific GPIB conditions or events. The status of these conditions can be
read from the ISR1 and ISR2 registers. The status bits in these registers function independently of
the corresponding mask bits; that is, they are set and cleared regardless of whether an interrupt
request is enabled for the condition. An important fact to remember is that ISR1 and ISR2 are
always cleared when read, even if the condition which caused the bit to be initially set remains true.
Data to and from the GPIB is pipelined through the CDOR and DIR respectively. An 8 MHz clock
is used as the CLOCK input to the TLC. For proper GPIB timing, the internal counter register must
be programmed to eight. The TLC RESET pin is driven by the GPIB-1014 RESET signal.
The AUXMR is used to issue special commands to the TLC and write to the five hidden registers.
The Parallel Poll Register (PPR) locally configures the TLC for polling. Auxiliary Registers A, B,
and E (AUXRA/B/E) provide a means to control a variety of diverse functions, such as enabling
handshake holdoffs, transmitting END when the EOS byte is sent, setting the END RX bit when
EOS is received, and enabling high speed transfers.
Two special purpose transceivers, a 75160 for the data signals and a 75162 for the handshake and
interface management signals, interface the TLC to the GPIB. Three signals from the TLC (T/R1
through T/R3) and the SC signal from the System Controller Select logic control signal direction of
these two transceivers. Controlling the direction of the data, handshake, and EOI signals, T/R1 is
high when the TLC is a Talker or Active Controller, and low when it is a Listener. Controlling the
direction of the ATN and SRQ signals, T/R2 is high when the TLC is Controller-In-Charge (CIC)
and low otherwise. T/R3 is high when the three-state driver mode is active and low when the open
collector mode is active. When the GPIB-1014P is parallel polled, the transceiver switches to open
collector mode. SC is set whenever the System Controller Select logic senses that the TLC has
received the Set IFC auxiliary command; SC is cleared when the TLC receives the Release System
Control auxiliary command. SC controls the direction of the IFC and REN signals, driving the
GPIB when SC is high and receiving from the GPIB when it is low.
