NAT-MCH Clock-PCB – Technical Reference Manual
Version 1.4
© N.A.T. GmbH
18
8 Functional
Blocks
The
NAT-MCH CLK Module
is divided into a number of functional blocks, which are
described in the following paragraphs.
8.1 Stratum 3 PLL
The ZL30105 supports the Telcordia GR-1244-CORE Stratum 3/4E/4 specification.
The ZL30105 accepts 3 different input references, and synchronizes to any combination
of 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz
inputs. One input is connected to the external reference clock input on the face plate; the
remaining two inputs are connected to the FPGA. By programming a FPGA register bit,
any clock signal from any AMC (either CLK1 or CLK2) or from the other NAT-MCH
(CLK1 or CLK3 update) can be connected to either of the two reference inputs of the
PLL. If no reference signal is available, the ZL30105 uses a 25 MHz master clock for
frequency generation in a free running mode. The 25 MHz clock is generated by an
oscillator.
The ZL30105 generates the following output frequencies:
•
1.544 MHz (T1)
•
2.048 MHz (E1)
•
3.088 MHz
•
16.384 MHz
•
19.44 MHz
(SDH)
•
4.096 MHz or 32.768 MHz
•
8.192 MHz or 65.536 MHz
•
6.312 MHz (DS2)
•
8.448 MHz (E2)
•
44.736 MHz (DS3)
•
34.368 MHz (E3)
•
2 kHz and
8 kHz
(frame pulses)
The different output signals are provided through different output pins of the
ZL30105[1]. These output pins are connected to the FPGA.
Also the different configuration inputs are connected to the FPGA or to the
microprocessor, and thus can be configured at runtime by application software.
The Zarlink PLL is only assembled if the TC-Option is chosen.
