N.A.T. NAT-MCH, Техническое справочное руководство

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NAT-MCH BASE-Module– Technical Reference Manual
Version 2.10 © N.A.T. GmbH 22
4.2.5 JP3: Development Connector
The BDM/JTAG-Port (also called COP header) can be used for debugging. It is
supported by major debug tool manufacturers.
Table 8: JP3: Development Connector – Pin Assignment
Pin # AMC-Signal AMC-Signal Pin #
1 /CPU_RSTOUT /BKPT 2
3 GND /DSCLK 4
5 GND SLV_TCK 6
7 /HRESET SLV_TDI 8
9 +3.3V CPU_TDO 10
11 GND PST_D7 12
13 PST_D6 PST_D5 14
15 PST_D4 PST_D3 16
17 PST_D2 PST_D1 18
19 PST_D0 JTAG_EN 20
21 NC NC 22
23 GND PST_CLK 24
25 TMREQ /TA 26
4.2.6 P3: External Clock Transceiver Module Connector
Connector P3 is used to connect the external clock transceiver module to the
NAT-MCH BASE-Module .
Table 9: P3: External Clock Transceiver Module Connector –
Pin Assignment
Pin # AMC-Signal AMC-Signal Pin #
1 SGND +3.3V 2
3 EXTREF_C_P EXTREF_CONF1 4
5 EXTREF_C_N EXTREF_CONF2 6
7 EXTREF_A_P EXTREF1_P 8
9 EXTREF_A_N EXTREF1_N 10
11 EXTREF_B_P EXTREF2_P 12
13 EXTREF_B_N EXTREF2_N 14
15 EXTREF_D_P EXTREF_CONF3 16
17 EXTREF_D_P SGND 18
19 EXTREF_CONF4 GND 20
4.2.7 SW1: Hot Swap Switch
Switch SW1 is used to support hot swapping of the module. It conforms to the
PICMG AMC.0 specification.
4.2.8 SW2: General Purpose DIL Switch
Switch SW2 is used for general purpose settings. It is an octal DIL switch and was
implemented for future use. SW2 is connected to the FPGA, by which its status
can be read.