N.A.T. NAT-AMC-ZYNQUP-FMC Скачать руководство пользователя

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NAT-AMC-ZYNQUP-FMC

ECHNICAL

EFERENCE

ANUAL

V1.1

UNCTIONAL

ESCRIPTION

- 17 -

4.2.

PLL and Clocking

The

NAT-AMC-ZYNQUP-FMC

features a SI5347 PLL, which is user-configurable by the FPGA

via I²C.

Figure 2

–

PLL and Clocking

Si5347

PLL

33.333MHz

Osc.

125MHz

Osc.

125MHz

Osc.

CLK_MGT_224

CLK_PS_REF

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

IN3

IN2

IN1

IN0

CLK_SI5347_FPGA

I2C_SCL_3V3

I2C_SDA_3V3

ZYNQUP

FPGA

Bank 223 / AH10

Bank 223 / AH9

Bank 226 / AA11

Bank 226 / AA12

CLK_MGT_223

CLK_MGT_226

Bank 227 / W12

Bank 227 / W11

CLK_MGT_227

CLK_MGT_228

Bank 227 / V10

Bank 227 / V9

CLK_DDR4

Bank 65 / AP14

Bank 65 / AR14

CLK_RAMCON

Bank 27 / G36

Bank 27 / G35

Bank 503 / AG28

Bank 224 / AF10

PCIe REFCLK 125MHz

Bank 224 / AF9

CLK_MGT_225

Ethernet REFCLK 125 MHz

Bank 225 / AD10
Bank 225 / AD9

CLK2_BIDIR

FP_CLK_REF_OUT

FMC Connector

Bank 87 / D10
Bank 87 / D11

H4
H5

C30

C31

CLK0_M2C_P

12.8 MHz

Stratum3 Ref CLK

AMC Connector

TCLKD

TCLKC

TCLKA

Bank 66 / AT5

Bank 66 / AT7

TCLKB

Bank 66 / AT6

Bank 66 / AT8

Bank 66 / AV7
Bank 66 / AV8

Bank 66 / AV6
Bank 66 / AU6

PS_MIO10

–

Bank 500 / Y28

PS_MIO11

–

Bank 500 / T30

I2C_SCL_3V3

I2C_SDA_3V3

75
74
78
77

135
136

138
139

FCLKA

Bank 224 / AE11
Bank 224 / AE12

PS System REFCLK 33.333MHz

CLK3_BIDIR

CLK1_M2C

Bank 87 / F10

Bank 87 / E10

Bank 87 / G11

Bank 87 / F11

Содержание NAT-AMC-ZYNQUP-FMC

Страница 1: ...chaft f r Netzwerk und Automatisierungs Technologie mbH Konrad Zuse Platz 9 53227 Bonn Germany Phone 49 228 965 864 0 sales nateurope com www nateurope com NAT AMC ZYNQUP FMC FMC CARRIER BOARD DESIGNE...

Страница 2: ...CK START 10 3 1 Unpacking 10 3 2 Mechanical Requirements 10 3 3 Voltage Requirements 11 3 3 1 POWER SUPPLY 11 3 3 2 HOT SWAP 11 4 FUNCTIONAL DESCRIPTION 12 4 1 SoC 12 4 1 1 PROCESSING SYSTEM CPU 12 4...

Страница 3: ...JTAG MUX SWITCH 48 5 3 10 SW4 BOOT MODE SELECT SWITCH 49 5 3 11 SW6 UART MUX 50 6 FMC OPERATION 51 6 1 Front panel 51 6 2 Supported FMC s 51 6 3 Installing a FMC Module 51 6 4 FMC EEPROM Wizard 52 7 K...

Страница 4: ...r 27 Table 11 J1C FMC Connector 28 Table 12 J1D FMC Connector 29 Table 13 J1E FMC Connector 31 Table 14 J1F FMC Connector 32 Table 15 J1G FMC Connector 33 Table 16 J1H FMC Connector 35 Table 17 J1I FM...

Страница 5: ...Figure 7 Location Diagram Bottom 22 Figure 8 J3 JTAG Programming Header 39 Figure 9 S1 AMC Connector top view 40 Figure 10 S2 MicroSD Card Slot 45 Figure 11 S3 USB UART Connector 46 Figure 12 SW2 FMC...

Страница 6: ...fits lost savings delays or interruptions in the flow of business activities including but not limited to special incidental consequential or other similar damages arising out of the use of or inabili...

Страница 7: ...ional Description Detailed information on the individual devices and the NAT AMC ZYNQUP FMC s main features Hardware Description of the connectors switches and LEDs located on the NAT AMC ZYNQUP FMC F...

Страница 8: ...plications 2 1 Applications An overview of the most common applications offered by the NAT AMC ZYNQUP FMC is given in the following paragraphs Beyond these customer applications are feasible as well 2...

Страница 9: ...USB JTAG connector JTAG over backplane connections Onboard Xilinx header connector FMC Slot Single HPC FMC slot VITA 57 1 compliant with limitations see chapter 5 3 1 HPC differential pairs LA HA HB a...

Страница 10: ...of TCA systems but can be plugged onto any ATCA carrier board supporting AMC standards as well So the installation requires an ATCA Carrier Board or an TCA Backplane for connecting the NAT AMC ZYNQUP...

Страница 11: ...plane carrier support hot swapping Ensure that the hot swap handle is in unlock position pulled out Push the NAT AMC ZYNQUP FMC carefully into the dedicated connector until it is completely inserted T...

Страница 12: ...O CLK_M2C DP0 DP9 CLK2_BIDIR_C2M GC CLK0_M2C Stratum III CLK_BIDIR Si5374 Clocking 4 1 SoC The central component on the NAT AMC ZYNQUP FMC is a Xilinx Zynq MPSoC Ultrascale FPGA device ZYNQUP This SoC...

Страница 13: ...s accompanied by up to 4GB DDR4 RAM x64 1600 2400Mb s The memory to FPGA pin assignment is shown in the tables below Table 2 DDR4 Memory to FPGA Pin Assignment Address CMD REFCLK RESET DDR4 Pin FPGA B...

Страница 14: ..._dq 10 AR25 DDR4_dq 42 AN18 DDR4_dqs_c 5 AP21 DDR4_dq 11 AP25 DDR4_dq 43 AN19 DDR4_dqs_t 6 AT21 DDR4_dq 12 AR24 DDR4_dq 44 AP17 DDR4_dqs_c 6 AU21 DDR4_dq 13 AP26 DDR4_dq 45 AL21 DDR4_dqs_t 7 AH19 DDR4...

Страница 15: ...GA Pin DDR4_B27_adr 16 F32 DDR4_B27_ba 0 F33 DDR4_B27_dm_n 0 D36 DDR4_B27_adr 15 G34 DDR4_B27_ba 1 F35 DDR4_B27_dq 0 C38 DDR4_B27_adr 14 G33 DDR4_B27_bg 0 F36 DDR4_B27_dq 1 C39 DDR4_B27_adr 13 H32 DDR...

Страница 16: ...adr 13 E30 DDR4_B28_bg 1 G28 DDR4_B27_dq 2 K28 DDR4_B28_adr 12 E29 DDR4_B28_cke 0 H28 DDR4_B27_dq 3 J29 DDR4_B28_adr 11 F31 DDR4_B28_cs_n 0 G29 DDR4_B27_dq 4 L27 DDR4_B28_adr 10 F30 DDR4_B28_odt 0 H29...

Страница 17: ...8 Bank 227 V10 Bank 227 V9 CLK_DDR4 Bank 65 AP14 Bank 65 AR14 CLK_RAMCON Bank 27 G36 Bank 27 G35 Bank 503 AG28 Bank 224 AF10 PCIe REFCLK 125MHz Bank 224 AF9 CLK_MGT_225 Ethernet REFCLK 125 MHz Bank 22...

Страница 18: ...d via I C The following figure shows the architecture in detail Figure 3 IPMB Interface MMC 0x61 Master PLL 0x6D FPGA SDA AJ12 SCL AK12 Temp 0x1E EEPROM 0x53 FPGA PS PL SDA PS_MIO11 SCL PS_MIO10 Custo...

Страница 19: ...aster is possible via the UART MUX Switch for detailed information on this switch please refer to chapter 5 3 11 SW6 UART MUX Figure 4 JTAG Architecture FPGA SoC AMC Connector JTAG MUX JTAG MUX Switch...

Страница 20: ...MC carrier board Figure 5 Front Panel Full Size HS Stat Flt NAT AMC ZYNQUP FMC 1 2 3 Table 6 LED Functionality LED Colour Function 1 User Red Green FPGA LED4 FPGA Pin AR4 VADJ FPGA LED5 FPGA Pin AR5 V...

Страница 21: ...rt Signal Basic Side Clocks CLK1 TCLKA Telecom Clock CLK2 TCLKB Telecom Clock CLK3 TCLKC Telecom Clock CLK4 TCLKD Telecom Clock CLK5 FCLKA Fabric Clock Common Options 0 GbE 1 2 Custom 3 Fat Pipe 4 PCI...

Страница 22: ...7 Location Diagram Bottom S1 MUX Power Supply Progr Module Zynq Atmel C S2 S3 Clock PLL PLL MUX Temp Power Supply SW3 SW6 SW2 EEPROM SW4 Connectors on top side drawings imply the board is orientated...

Страница 23: ...M_P GND HA01_CC_P GND CLK1_M2C_P FMC_PRSNT_ M2C_L CLK3_BIDIR_P GND 3 DP1_M2C_N GND DP0_C2M_N GND HA01_CC_N GND CLK1_M2C_N GND CLK3_BIDIR_N GND 4 GND DP9_M2C_P GND GBTCLK0_M 2C_P GND HA00_CC_P GND CLK0...

Страница 24: ..._M2 C_N GND LA17_CC_N HB03_P GND LA20_P GND HA22_P GND 22 DP1_C2M_P GND LA18_CC_P GND HB03_N HB02_P LA20_N LA19_P HA22_N HA23_P 23 DP1_C2M_N GND LA18_CC_N LA23_P GND HB02_N GND LA19_N GND HA23_N 24 GN...

Страница 25: ...35 DP4_C2M_N GND 12POV FSIG_GA1 GND HB16_N GND LA30_N GND HB14_N 36 GND DP6_C2M_P GND 3P3V HB21_P GND LA33_P GND HB18_P GND 37 GND DP6_C2M_N 12POV GND HB21_N HB20_P LA33_N LA32_P HB18_N HB17_CC_P 38 D...

Страница 26: ...3 GND GND A14 DP4_M2C_P DP4_M2C_P 227 1V2_ MGTA VTT MGTHRXP3_227 N4 A15 DP4_M2C_N DP4_M2C_N MGTHRXN3_227 N3 A16 GND GND A17 GND GND A18 DP5_M2C_P DP5_M2C_P 227 1V2_ MGTA VTT MGTHRXP2_227 P2 A19 DP5_M2...

Страница 27: ...GND B7 GND GND B8 DP8_M2C_P DP8_M2C_P 226 1V2_ MGTA VTT MGTHRXP3_226 U4 B9 DP8_M2C_N DP8_M2C_N MGTHRXN3_226 U3 B10 GND GND B11 GND GND B12 DP7_M2C_P DP7_M2C_P 227 1V2_ MGTA VTT MGTHRXP0_227 T2 B13 DP7...

Страница 28: ...AMC ZYNQUP FMC Label FPGA Bank VCCO FPGA Pin Name FPGA Pin C1 GND GND C2 DP0_C2M_P DP0_C2M_P 228 1V2_ MGTA VTT MGTHTXP3_228 J8 C3 DP0_C2M_N DP0_C2M_N MGTHTXN3_228 J7 C4 GND GND C5 GND GND C6 DP0_M2C_...

Страница 29: ...MIO11 T30 C32 GND GND C33 GND GND C34 GA0 FMC_GA0 C35 12POV 12POV C36 GND GND C37 12POV 12POV C38 GND GND C39 3P3V 3P3V C40 GND GND Table 12 J1D FMC Connector FMC Pin FMC Label NAT AMC ZYNQUP FMC Labe...

Страница 30: ...D20 LA17_P_CC LA17_CC_P 68 VADJ IO_L11P_T1U_N8_GC_ 68 F21 D21 LA17_N_CC LA17_CC_N IO_L11N_T1U_N9_GC_ 68 F22 D22 GND GND D23 LA23_P LA23_P 68 VADJ IO_L3P_T0L_N4_AD15 P_68 B21 D24 LA23_N LA23_N IO_L3N_...

Страница 31: ...E13 HA13_N HA13_N IO_L9N_T1L_N5_AD12 N_67 H16 E14 GND GND E15 HA16_P HA16_P 67 VADJ IO_L4P_T0U_N6_DBC_ AD7P_67 L17 E16 HA16_N HA16_N IO_L4N_T0U_N7_DBC_ AD7N_67 L16 E17 GND GND E18 HA20_P HA20_P 66 VA...

Страница 32: ...T2L_N3_GC_ 67 G18 F6 GND GND F7 HA04_P HA04_P 67 VADJ IO_L16P_T2U_N6_QBC _AD3P_67 E19 F8 HA04_N HA04_N IO_L16N_T2U_N7_QB C_AD3N_67 E18 F9 GND GND F10 HA08_P HA08_P 67 VADJ IO_L15P_T2L_N4_AD1 1P_67 F18...

Страница 33: ...1N_AD15N_88 L12 F36 GND GND F37 HB20_P HB20_P nc F38 HB20_N HB20_N nc F39 GND GND F40 VADJ Vadj Table 15 J1G FMC Connector FMC Pin FMC Label NAT AMC ZYNQUP FMC Label FPGA Bank VCCO FPGA Pin Name FPGA...

Страница 34: ...D8 N_67 C16 G23 GND GND G24 LA22_P LA22_P 68 VADJ IO_L9P_T1L_N4_AD12 P_68 D21 G25 LA22_N LA22_N IO_L9N_T1L_N5_AD12 N_68 D22 G26 GND GND G27 LA25_P LA25_P 67 VADJ IO_L20P_T3L_N2_AD1 P_67 B19 G28 LA25_N...

Страница 35: ...D H13 LA07_P LA07_P 68 VADJ IO_L8P_T1L_N2_AD5P _68 F25 H14 LA07_N LA07_N IO_L8N_T1L_N3_AD5N _68 E25 H15 GND GND H16 LA11_P LA11_P 67 VADJ IO_T2U_N12_67 D19 H17 LA11_N LA11_N IO_T3U_N12_67 D20 H18 GND...

Страница 36: ...J2 CLK3_BIDIR_P CLK3_BIDIR_P 87 VIO_B _M2C IO_L6P_HDGC_AD6P_ 87 F10 J3 CLK3_BIDIR_N CLK3_BIDIR_N IO_L6N_HDGC_AD6N_ 87 E10 J4 GND GND J5 GND GND J6 HA03_P HA03_P 67 VADJ IO_L2P_T0L_N2_67 N19 J7 HA03_N...

Страница 37: ...J33 HB15_P HB15_P 87 VIO_B _M2C IO_L4P_AD8P_87 H11 J34 HB15_N HB15_N IO_L4N_AD8N_87 G10 J35 GND GND J36 HB18_P HB18_P 87 VIO_B _M2C IO_L1P_AD11P_87 K10 J37 HB18_N HB18_N IO_L1N_AD11N_87 J10 J38 GND G...

Страница 38: ...AP2 K23 HA23_N HA23_N IO_L6N_T0U_N11_AD6 N_66 AP1 K24 GND GND K25 HB00_P_CC HB00_CC_P 88 VIO_B _M2C IO_L6P_HDGC_88 G15 K26 HB00_N_CC HB00_CC_N IO_L6N_HDGC_88 F15 K27 GND GND K28 HB06_P_CC HB06_CC_P 8...

Страница 39: ...Signal Signal Pin 1 V_PROG JTAG_DISABLE 2 3 FPGA_TMS GND 4 5 FPGA_TCK GND 6 7 FPGA_TDO GND 8 9 FPGA_TDI GND 10 11 nc GND 12 13 PS_ARM_SRST GND 14 5 3 3 J6 Memory Connector Connector J6 offers the opti...

Страница 40: ...Label NAT AMC ZYNQUP FMC Label FPGA Bank VCCO FPGA Pin Name FPGA Pin 1 GND GND 2 PWR 12V_PP 3 PS1 AMC_PS1 4 MP 3 3V_MP 5 GA0 AMC_GA0 6 RSVD6 nc 7 GND GND 8 RSVD8 nc 9 PWR 12V_PP 10 GND GND 11 TX0 POR...

Страница 41: ...L_N0_DBC _AD9P_66 AP9 33 RX2 PORT2 Rx_N IO_L19N_T3L_N1_DBC _AD9N_66 AP8 34 GND GND 35 TX3 PORT3 Tx_P 66 VADJ IO_L23P_T3U_N8_66 AK10 36 TX3 PORT3 Tx_N IO_L23N_T3U_N9_66 AL10 37 GND GND 38 RX3 PORT3 Rx_...

Страница 42: ...1V2_ MGTA VTT MGTHTXP0_224 AH6 66 TX7 PORT7 Tx_N MGTHTXN0_224 AH5 67 GND GND 68 RX7 PORT7 Rx_P 224 1V2_ MGTA VTT MGTHRXP0_224 AH2 69 RX7 PORT7 Rx_N MGTHRXN0_224 AH1 70 GND GND 71 SDA AMC_SDA 72 PWR 1...

Страница 43: ...P MGTHTXP2_223 AK6 98 GND GND 99 RX10 PORT10 Rx_N 223 1V2_ MGTA VTT MGTHRXN1_223 AL3 100 RX10 PORT10 Rx_P MGTHRXP1_223 AL4 101 GND GND 102 TX10 PORT10 Tx_N 223 1V2_ MGTA VTT MGTHTXN1_223 AL7 103 TX10...

Страница 44: ...5 PORT15 Tx_N 226 1V2_ MGTA VTT MGTHTXN1_226 W7 133 TX15 PORT15 Tx_P MGTHTXP1_226 W8 134 GND GND 135 TCLKC AMC_TCLKC_N 66 VADJ IO_L12N_T1U_N11_GC _66 AV7 136 TCLKC AMC_TCLKC_P IO_L12P_T1U_N10_GC _66 A...

Страница 45: ...RX20 PORT20 Rx_P IO_L3P_T0L_N4_AD15 P_66 AR2 161 GND GND 162 TX20 PORT20 Tx_N 163 TX20 PORT20 Tx_P 164 GND GND 165 TCK AMC_TCK 166 TMS AMC_TMS 167 TRST nc 168 TDO AMC_TDO 169 TDI AMC_TDI 170 GND GND...

Страница 46: ...3 6 S3 USB UART Connector The NAT AMC ZYNQUP FMC features an USB UART interface via a Micro USB connector at the front panel Figure 11 S3 USB UART Connector 1 5 Table 23 S3 USB UART Connector Pin Ass...

Страница 47: ...erating parameters and configuration options of SW2 Figure 12 SW2 FMC Configuration Switch 1 2 OFF ON Table 24 SW2 Operating Parameters Switch Function SW2 1 Reserved for future SW2 2 FMC record gener...

Страница 48: ...13 SW3 JTAG MUX Switch 1 2 OFF ON Table 26 SW3 Operating Parameters Switch Function SW3 1 JTAG Select FPGA or JTAG SMT3 module as Master SW3 2 JTAG Disable Table 27 SW3 Configuration Switch ON OFF SW3...

Страница 49: ...lect Switch The tables below provide information on the operating parameters and configuration options of SW4 Figure 14 SW4 Boot Mode Select Switch 1 2 OFF ON Switch SW4 determines the boot mode of th...

Страница 50: ...parameters and configuration options of SW6 Figure 16 SW6 UART MUX 1 2 OFF ON Table 28 SW6 Operating Parameters Switch Function SW6 1 UART Select SW6 2 UART Disable Table 29 SW6 Configuration Switch...

Страница 51: ...N A T in case specialized front panel needs to be made 6 2 Supported FMC s All FMCs compliant to VITA 57 1 are supported including region 1 2 and 3 FMC modules VADJ and VIO_B_M2C are limited to 1 8V P...

Страница 52: ...Ignore the FRU EEPROM This is automatically done when no valid FRU content is detected Warning In this case a default VADJ voltage of 1 8V is applied to the FMC module Please check the capabilities o...

Страница 53: ...e The console output should output the following line Press any key to generate FMC FRU file 5 0 Within five seconds time press any key to enter the FMC programming mode This mode is guided and will l...

Страница 54: ...MANUAL V1 1 KNOWN ISSUES 54 7 KNOWN ISSUES PCB V1 0 has the following known issues LA27 LA21 LA11 HA06 cannot be used for differential pair operation Clock Direction of CLK2_BIDIR is fixed at C2M HA14...

Страница 55: ...e AMC 0 R2 0 AMC 1 AMC 2 AMC 3 AMC 4 IMPI V1 5 HPM 1 8 4 Compliance to RoHS Directive Directive 2011 65 EU of the European Parliament and of the Council of 8 June 2011 on the Restriction of the use of...

Страница 56: ...the directive also affects business to business relationships The directive is quite restrictive on how such waste of private persons and households has to be handled by the supplier manufacturer howe...

Страница 57: ...Unit DAC Digital Analog Converter DDR4 SDRAM Double Data Rate Synchronous DRAM D RAM Dynamic Random Access Memory eMMC Embedded Multimedia Card FCLK Fabric Clock FMC FPGA Mezzanine Card FPGA Field Pr...

Страница 58: ...COMPLIANCES 58 Abbreviation Description SAS Serial Attached SCSI SATA Serial Advanced Technology Attachment SDR Software Defined Radio SoC System on a Chip SRIO Serial Rapid I O TCKL Telecom Clock UAR...

Страница 59: ...d FMC Signal routing information Added PLL Clocking information se 29 04 2020 Minor changes mm 1 1 20 01 2021 Updated Block Diagram in chapter 4 Functional Description Updated chapter 4 1 2 Programmab...

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