\\\\\\\\\\\\
O P E RAT I O N
O P E RAT I O N
O P E RAT I O N
> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > >
88
Manual SDs-01 E 6.2.2003 18:18 Uhr Seite 13
15
AES/EBU ID
OUT
Function Area
This function area enables to change the output level of the AES/EBU ID
outputs from 1V peak – peak, which is the standard aligned to AES 3 ID, to
3V peak – peak. The level change can be activated in all operation modes of
MC-2.
The factory default setting is 1 VOLT
PP
.
STATUS Status Area
This area displays the status of the internal low-jitter PLL circuit.
LOCK
When the LOCK LED lights, the PLL circuit is locked to the external digital
audio or sync reference signal. This signal will be processed and transfered
like described previously to all corresponding outputs. The four LEDs of the
CLOCK IN status area will display the clock rate of the reference signal.
NO REF
When the NO REF LED lights, the PLL circuit is not locked to an external
digital audio or sync reference signal. This can be caused by a missing
or absent reference as well as by an extremely unstable or interrupted
reference signal. All outputs are muted, no LED of the CLOCK IN status area
will light.
CLOCK
IN
Status Area
This area displays the clock rate of the incoming digital audio or sync
reference signal. The following rates are supported and will be analyzed
32.0 kHz
44.1 kHz
48.0 kHz
88.2 kHz
96.0 kHz
176.4 kHz
192.0 kHz
These indications are only available if the internal PLL circuit is locked stably
to the external reference signal and the corresponding blue LOCK-LED
lights permanently.
Example
This function can be useful if AES 3 ID signals
need to be transfered about very long dis-
tances to ensure to have enough signal level
for the input circuits of the receiving devices
available.
