1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
D
D
C
C
B
B
A
A
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2
19
HD Connectors female
AKX00032
V1.1
2021-05-11
15:10:53
Title:
ID:
Date:
Revision:
Sheet
of
Time:
S.Navaretti
Author:
RevAuthor:
*
HDConn_FEMALE.SchDoc
File:
J1
DF40HC(3.5)-80DS-0.4V(51)-LEFT
J2
DF40HC(3.5)-80DS-0.4V(51)-RIGHT
VREF_P
A0
A1
A2
A3
A7
A6
A5
A4
VREF_N
ANALOG
0
1
2
3
4
5
6
7
8
9
PWM
0
1
2
3
4
5
6
GPIO
A_P
A_N
B_P
B_N
C_P
C_N
D_P
D_N
LED1
LED2
ETH
VBUS
D_P
D_N
ID
USB
RX
TX
RTS
CTS
UART
SCL
SDA
I2C
RX
TX
CAN
CLK
CMD
D0
D1
D2
D3
CD
WP
RST
SDC
RESET
TCK/SCK
TDI
TDO/SWO
TMS/SWD
TRST
JTAG
CLK_N
CLK_P
D0_N
D0_P
D1_N
D1_P
D2_N
D2_P
D3_N
D3_P
DISPLAY
VBUS
D_P
D_N
ID
USB
RX
TX
RTS
CTS
UART
SDA
SCL
I2C
CK
SDI
SDO
WS
I2S
CK
D0
D1
PDM
RX
TX
RTS
CTS
UART
SDA
SCL
I2C
CK
FS
D0
D1
SAI
D7_D3_P
D6_D3_N
D5_D2_P
D4_D2_N
D3_D1_P
D2_D1_N
D1_D0_P
D0_D0_N
VS_CK_P
CK_CK_N
HS
CAMERA
RX
TX
RTS
CTS
UART
CS
CK
MISO
MOSI
SPI
SHARED
PINS
SHARED
PINS
SHARED PINS TABLE
BUS 1
JTAG
PB3
SDC2
PH12
I2C4
CAM
PH11
I2C4
CAM
PA6
ANALOG
CAM
PA4
ANALOG
CAM
PC3
PC2
ANALOG
ANALOG
SPI2
SPI2
SAI2A
SAI2A
SAI2A
CAM
CAM
CAM
PI6
PI5
PI7
SHARED
PINS
SHARED
PINS
SHARED
PINS
SHARED
PINS
BUS 2
NET
VSYS
VIN
VIN
PJ6
DSI_CK_P
DSI_CK_N
DSI_D0_P
DSI_D0_N
DSI_D1_P
DSI_D1_N
PA0
PI9
PI10
PI13
PE2
PB2
NRST
PA13
PA14
PD6
PD7
PB14
PB15
PB4
PB7
PB6
PI14
PI15
PA9
PA10
VIN
PH8
PH7
PD3
PB9
PI2
PI3
VSYS
VCC
VIN
HSU_D_N
HSU_D_P
ETH_A_P
ETH_A_N
ETH_B_P
ETH_B_N
USB0_D_P
VCC
VCC
VCC
VCC
PC2
PI1
PI0
PC3
PC13
PC15
PD4
PD5
PE3
PG3
PG10
PH12
PH11
PA6
PI5
PH9
PH10
PH14
PI4
PI6
PG14
PG9
PK1
PH15
PJ7
PJ10
PH6
PA0_C
PA1_C
PC2_C
PC3_C
PA4
PA8
PC6
PC7
PG7
PJ11
PK1
PH15
PJ7
PJ10
PH6
PJ9
PJ8
IF NECESSARY ROUTE CAMERA
WITH DIFFERENTIAL PAIR RULES
CHANGING THE NET NAMES.
REFER TO SHARED PINS TABLE
= PA12
= PA11
USB0_D_N
LICELL
USB
J1
J2
1
1
80
80
Portenta
J1
J2
USB
J1
J2
1
1
80
80
J1
J2
BOTTOM
view
Carrier
TOP
view
Portenta
SIDE
view
Carrier
SIDE
view
HD Connectors on the carrier are mirrored
J2
J1
1
80
80
1
80
1
1
80
J1
J2
USB
Portenta
Carrier
POWER NETS TABLE
TYPE
NET
VCC
VSYS
VIN
PORTENTA INPUT
PORTENTA OUTPUT
PORTENTA RESERVED
OUTPUT
RANGES
DESCRIPTION
4.1V to 6V.
1.1V to 3.3V in steps, max 1A.
Default 3.3V, PMIC (U10) programmable output.
RESERVED, DO NOT USE
Default 4.2V, PMIC (U10) programmable output which is also
the input voltage of the bucks inside the PMIC itself.
Default 3.3V, PMIC (U10) programmable output.
LICELL
PORTENTA INPUT
Coinc cell max 3.6V, max 46uA.
Max 4uA with PMIC (U10) in coin cell mode, max 46uA with
PMIC in standby/suspend mode.
3.5V to 4.2V, max 600mA.
RX
TX
CAN
CAN0
CAN0 NOT
CONNECTED ON H7
SPI0 NOT
CONNECTED ON H7
CS
CK
MISO
MOSI
SPI
SPI0
PCIE NOT
CONNECTED ON H7
TX_P
TX_N
RX_P
RX_N
CK_P
CK_N
RST
PCIE
PCIE
SPDIF NOT
CONNECTED ON H7
SPDIF
RX
TX
SPDIF
ETH_C_P
ETH_C_N
ETH_D_P
ETH_D_N
ETH pair C and D
are not connected
on H7
PB8
PH13
= PB3
= PB3
= PA6
= PC3
= PC2
= PA4
= PI5
= PI7
= PH12
= PH11
PI7
= PI6
