Motorola XTL 1500, Подробное руководство по обслуживанию

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June 15, 2005 6815854H01-A
3-26 Theory of Operation: Receiver Back-End
3.11.2.2.1 Second Local Oscillator (LO)
The ABACUS III IC local oscillator (LO) synthesizer controls the second LO. Signal FREF is the
16.8 MHz reference from the frequency generation unit (FGU). The second LO frequency is
107.4 MHz by default, or 111.9 MHz in special cases as necessary to avoid radio self-quieters. The
second LO signal mixes with IFIN to produce a 2.25 MHz final IF. The external VCO consists of
transistor Q5002, together with its bias and instability network and tank elements. Darlington
transistor Q5001 along with C5018 and C5050 form an active DC filter. The 2nd order loop filter is
comprised of C5044, C5045, and R5013.
3.11.2.2.2 Sampling Clock Oscillator
The ABACUS III IC sampling clock synthesizer, at Fclk=18 MHz (IF2=Fclk/8, where Fclk is the clock
rate), utilizes the clock VCO built around Q5003.
3.11.3 UHF Range 2 (450-520 MHz) Band
The receiver back-end (see Figure 3-16 on page 3-20 ) contains the following major components:
• Intermediate frequency (IF) filter
• ABACUS III IC
3.11.3.1 Intermediate Frequency (IF) Filter
The XTL 1500 radio uses two leadless, surface-mount, two-pole, third-overtone, quartz crystal filters
(Y5400, Y5401) separated by a 20 dB gain IF amplifier. The filter is centered at 109.65 MHz. This
narrow-bandpass filter gives the radio part of its adjacent-channel and alternate-channel rejection
performance. Impedance-matching networks are located at the input and output of each crystal. The
IF amplifier is made with Q5401. The 10 dB attenuator (U5400) located after the second crystal filter
is controlled by the software to limit the signal gain in front of the ABACUS III IC.
3.11.3.2 ABACUS III IC (U5002)
The receiver back-end is designed around the ABACUS III (AD9874 IF digitizing subsystem) IC and
its associated circuitry. The AD9874 (
Figure 3-20 on page 3-27 ) is a general-purpose, IF subsystem
that digitizes a low-level, 10-300 MHz IF input with a bandwidth up to 270 kHz. The signal chain of
the AD9874 consists of a variable gain, low-noise amplifier, a mixer; a bandpass, sigma-delta, A/D
converter; and a decimation filter with programmable decimation factor. An automatic gain control
(AGC) circuit provides the AD9874 with 12 dB of continuous gain adjustment. The high dynamic
range and inherent anti-aliasing provided by the bandpass, sigma-delta converter allow the AD9874
to cope with blocking signals 80 dB stronger than the desired signal. Auxiliary blocks include clock
and LO synthesizers, as well as an SPI port. Input signal RXIF is the 109.65 MHz IF from the IF filter.
Components C5002, C5007, and L5002 match the input impedance from 50 ohms (IF Filter
terminating impedance) to the ABACUS III IC input IFIN. Formatted SSI (synchronous serial
interface) data is output to the Patriot microcontroller IC for DSP processing on ports FS, DOUTA,
and CLKOUT. Control logic is sent to the ABACUS III IC from the Patriot microcontroller via the SPI
lines (PC, PD, PE).