Motorola PPC/CPCI-690, Справочное руководство

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Interrupt Map Maps and Registers
6 - 8 PPC/CPCI-690
External Interrupt Sources
The following GPP pins of the system controller are used to connect exter-
nal interrupts to the internal interrupt controller. For a correct functionality,
the GPP pins must be configured according to “System Controller MPP
Configuration” page 6-7.
[8] GNT0[4]# PCI bus 0 GNT# Output Active low
[7] REQ1[3]# PCI bus 1 REQ# Input Active low
[6] GNT1[3]# PCI bus 1 GNT# Output Active low
[5] REQ1[2]# PCI bus 1 REQ# Input Active low
[4] GNT1[2]# PCI bus 1 GNT# Output Active low
[3] REQ1[1]# PCI bus 1 REQ# Input Active low
[2] GNT1[1]# PCI bus 1 GNT# Output Active low
[1] REQ1[0]# PCI bus 1 REQ# Input Active low
[0] GNT1[0]# PCI bus 1 GNT# Output Active low
Table 29: System Controller MPP Configuration (cont.)
MPP Function Description Direction Polarity
Table 30: External Interrupt Sources
GPP Interrupt Description Source Polarity
[31]
[30]
[29]
[28] PCI1_INTD#
PCI1_INTC#
PCI1_INTB#
PCI1_INTA# Shared PCI interrupts
from PCI bus 1 See “PCI Bus 1”
page 5-12 Active low
[27]
[26]
[25]
[24] PCI0_INTD#
PCI0_INTC#
PCI0_INTB#
PCI0_INTA# Shared PCI interrupts
from PCI bus 0 See “PCI Bus 0”
page 5-8 Active low
[23] WDNMI# NMI# interrupt from sys-
tem controller’s internal
watchdog Watchdog Active low
[21]
[20]
[19] IPMI_IRQ2
IPMI_IRQ1
IPMI_IRQ0 Interrupts from the on-
board IPMI controller IPMI controller Active
high