4-4
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Functional Description
4
ASICs
The following ASICs are used on the MVME172P4:
❏
VMEchip2 ASIC (VMEbus interface). Provides two tick timers, a
watchdog timer, programmable map decoders for the master and
slave interfaces, and a VMEbus to/from local bus DMA controller
as well as a VMEbus to/from local bus non-DMA programmed
access interface, a VMEbus interrupter, a VMEbus system
controller, a VMEbus interrupt handler, and a VMEbus requester.
Processor-to-VMEbus transfers are D8, D16, or D32. VMEchip2
DMA transfers to the VMEbus, however, are D16, D32, D16/BLT,
D32/BLT, or D64/MBLT.
❏
Petra ASIC. Combines the functions previously covered by the
MC2 chip, the MCECC chip, and the IP2 chip in a single ASIC.
– MC2 function. Provides a parity DRAM emulation. Also
supplies four tick timers and interfaces to the LAN chip, SCSI
chip, serial port chip, BBRAM, EPROM/Flash, and SRAM.
– MCECC function. Provides an ECC DRAM emulation.
– IP2 function. Provides control and status information for up to
four single-wide or two double-wide IndustryPack modules that
can be plugged into the MVME172P4 main board.
Block Diagram
The block diagram in
Figure 4-1 on page 4-5
illustrates the
MVME172P4’s overall architecture.
Functional Description
This section contains a functional description of the major blocks on the
MVME172P4.
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