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Hardware Preparation and Installation
1
System Considerations
The MVME172P4 draws power from VMEbus backplane connectors P1
and P2. P2 is also used for the upper 16 bits of data in 32-bit transfers, and
for the upper 8 address lines in extended addressing mode. The
MVME172P4 may not operate properly without its main board connected
to VMEbus backplane connectors P1 and P2.
Whether the MVME172P4 operates as a VMEbus master or VMEbus
slave, it is configured for 32 bits of address and 32 bits of data (A32/D32).
However, it handles A16 or A24 devices in the address ranges indicated in
the VMEchip2 chapter of the Programmer’s Reference Guide. D8 and/or
D16 devices in the system must be handled by the MC680x0/MC68LC0x0
software. For specifics, refer to the memory maps in the Programmer’s
Reference Guide.
The MVME172P4 contains shared onboard DRAM whose base address is
software-selectable. Both the onboard processor and offboard VMEbus
devices see this local DRAM at base physical address $00000000, as
programmed by the MVME172Bug firmware. This may be changed via
software to any other base address. Refer to the Programmer’s Reference
Guide for more information.
If the MVME172P4 tries to access offboard resources in a nonexistent
location and is not system controller, and if the system does not have a
global bus timeout, the MVME172P4 waits forever for the VMEbus cycle
to complete. This will cause the system to lock up. There is only one
situation in which the system might lack this global bus timeout: when the
MVME172P4 is not the system controller and there is no global bus
timeout elsewhere in the system.
Multiple MVME172P4s may be installed in a single VME chassis. In
general, hardware multiprocessor features are supported.
Note
If you are installing multiple MVME172P4s in an MVME945
chassis, do not install an MVME172P4 in slot 12. The height of
the IP modules may cause clearance difficulties in that slot
position.
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