Preparing the Board
http://www.motorola.com/computer/literature
1-21
1
MCECC DRAM Size (S6)
MVME1x2P4 boards use SDRAM (Synchronous DRAM) in place of
DRAM. The MVME172P4’s 16MB shared SDRAM is configurable to
emulate either of the following memory models:
❏
1MB, 4MB, 8MB, or 16MB shared parity-protected DRAM
❏
4MB, 8MB, or 16MB ECC-protected DRAM
The two memory controllers modeled in the Petra ASIC duplicate the
functionality of the “parity memory controller” found in MC2 ASICs as
well as that of the “single-bit error correcting/double-bit error detecting”
memory controller found in MCECC ASICs. Board firmware will
initialize the memory controller as appropriate.
If the Petra ASIC is supporting MVME1x2P4 functionality, firmware will
enable the parity (MC2) memory controller model. If the Petra ASIC is
supporting MVME1x2P2 functionality, firmware will enable either the
parity or the MCECC memory controller model, depending on the board
configuration. Board configuration is a function of switch settings and
resistor population options.
S6 comes into play in the MCECC memory controller model. S6 is a four-
segment slide switch whose lower three segments establish the size of the
ECC DRAM (segment 4 is not used.) Refer to the illustration and table
below for specifics.
.
2737 0004
ON
OFF
4
1
S6
16MB MCECC DRAM
(factory configuration )
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