5-1
5
5
MCECC
Introduction
This chapter describes the ECC DRAM Controller ASIC (MCECC) used
on the memory mezzanine boards with ECC protection. The MCECC is
designed for the 200/300-Series MVME172 boards and is used in a set of
two, to provide the interface to a 144-bit wide DRAM memory system.
Note that the 400/500-Series MVME172 does not contain this chip.
Features
❏
Allows 2-1-1-1 memory accesses (sustained) for burst writes
❏
Allows 4-1-1-1 memory accesses (sustained) for burst reads (5-1-1-
1 with BERR on or when FSTRD is cleared)
❏
Supports byte, two-byte, four-byte, and cache line read or write
transfers
❏
Programmable base address for DRAM
❏
Built-in refresh timer and refresh controller
❏
ECC
– Single Bit Error Detect and Correct
– Software enabled Interrupt on Single Bit Error
– Address and Syndrome Register For Single Bit Error Logging
Support
– Double Bit Error Detect
– Software programmable Bus Error and/or Interrupt on Double
Bit Error
❏
Programmable period automatic scrub operation
Содержание MVME172
Страница 1: ...MVME172 VME Embedded Controller Programmer s Reference Guide VME172A PG2 Edition of February 1999 ...
Страница 6: ...Place holder ...
Страница 18: ...xviii ...
Страница 78: ...1 60 Computer Group Literature Center Web Site Board Description and Memory Maps 1 ...
Страница 332: ...5 42 Computer Group Literature Center Web Site MCECC 5 ...
Страница 336: ...A 4 Related Documentation A ...
Страница 340: ...VMEchip2 Tick Timer 1 Periodic Interrupt Example B 4 Computer Group Literature Center Web Site B ...
Страница 352: ...Index IN 12 Computer Group Literature Center Web Site I N D E X ...
Страница 354: ......