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Functional Description
4
The SDRAM memory array itself is always a single-bit error correcting
and multi-bit error detection memory, irrespective of which interface
model you use to access the SDRAM. When the MC2 (parity) memory
controller interface is used to access the SDRAM, single-bit errors are
undetectable to users and multi-bit errors are defined to be parity errors.
Firmware will initialize the memory controller to maintain backward
compatibility with MVME162LX or -FX products. If the Petra ASIC is
supporting MVME162FX functionality, the parity memory controller
model will be enabled by default. If the Petra ASIC is supporting
MVME162LX functionality, firmware will enable either the parity or the
ECC memory controller model, depending on board configuration. (The
board configuration is a function of switch settings and resistor population
options.)
User code can modify Petra register settings to operate in either mode.
User code can also modify map decoder/switch settings to enable the
maximum amount of memory available. The minimum SDRAM
configuration is 16MB.
For specifics on SDRAM performance and for detailed programming
information, refer to the chapters on MC2 and MCECC memory controller
emulations in the MVME1X2P2 VME Embedded Controller
Programmer’s Reference Guide.
SRAM
The MVME162P2 implementation includes a 512KB SRAM (static
RAM) option. SRAM architecture is single non-interleaved. SRAM
performance is described in the section on the SRAM memory interface in
the chapter on the MC2 memory controller emulation in the MVME1X2P2
VME Embedded Controller Programmer’s Reference Guide. An onboard
battery supplies VCC to the SRAM when main power is removed. The
SRAM arrays are not parity protected.
The battery backup function for the onboard SRAM is provided by a coin-
type Panasonic CR2032 device (or equivalent)
that supports primary and
secondary power sources. In the event of a main board power failure, the
CR2032 checks power sources and switches to the source with the higher
voltage.
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