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1-10 MPC8240 Integrated Processor User’s Manual
Peripheral Logic Bus
1.3 Peripheral Logic Bus
The MPC8240 contains an internal peripheral logic bus that interfaces the processor core
to the peripheral logic. The core can operate at a variety of frequencies allowing the
designer to balance performance and power consumption. The processor core is clocked
from a separate PLL, which is referenced to the peripheral logic PLL. This allows the
microprocessor and the peripheral logic to operate at different frequencies while
maintaining a synchronous bus interface.
The processor core-to-peripheral logic interface includes a 32-bit address bus, a 32- or
64-bit data bus as well as control and information signals. The peripheral logic bus allows
for internal address-only transactions as well as address and data transactions. The
processor core control and information signals include the address arbitration, address start,
address transfer, transfer attribute, address termination, data arbitration, data transfer, data
termination, and processor state signals. Test and control signals provide diagnostics for
selected internal circuits.
The peripheral logic interface supports bus pipelining, which allows the address tenure of
one transaction to overlap the data tenure of another. PCI accesses to the memory space are
monitored by the peripheral logic bus to allow the processor to snoop these accesses (when
snooping not explicitly disabled).
As part of the peripheral logic bus interface, the processor core’s data bus is configured at
power-up to either a 32- or 64-bit width. When the processor is configured with a 32-bit
data bus, memory accesses on the peripheral logic bus interface allow transfer sizes of 8,
16, 24, or 32 bits in one bus clock cycle. Data transfers occur in either single-beat
transactions, or two-beat or eight-beat burst transactions, with a single-beat transaction
transferring as many as 32 bits. Single- or double-beat transactions are caused by
noncached accesses that access memory directly (that is, reads and writes when caching is
disabled, caching-inhibited accesses, and stores in write-through mode). Eight-beat burst
transactions, which always transfer an entire cache line (32 bytes), are initiated when a line
is read from or written to memory.
When the peripheral logic bus interface is configured with a 64-bit data bus, memory
accesses allow transfer sizes of 8, 16, 24, 32, or 64 bits in one bus clock cycle. Data transfers
occur in either single-beat transactions or four-beat burst transactions. Single-beat
transactions are caused by noncached accesses that access memory directly (that is, reads
and writes when caching is disabled, caching-inhibited accesses, and stores in
write-through mode). Four-beat burst transactions, which always transfer an entire cache
line (32 bytes), are initiated when a block is read from or written to memory.