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7-14 MPC8240 Integrated Processor User’s Manual
PCI Bus Transactions
If the MPC8240, as a target, detects no byte enables asserted, it completes the current data
phase with no permanent change. This implies that on a read transaction the MPC8240
expects that the data is not changed, and on a write transaction, that ‘the data is not stored.
7.3.6 Bus Driving and Turnaround
To avoid contention, a turnaround cycle is required on all signals that may be driven by
more than one agent. The turnaround cycle occurs at different times for different signals.
The IRDY, TRDY, DEVSEL, and STOP signals use the address phase as their turnaround
cycle. FRAME, C/BE[3:0], and AD[31:0] signals use the idle cycle between transactions
(when both FRAME and IRDY are negated) as their turnaround cycle. The PERR signal
has a turnaround cycle on the fourth clock after the last data phase.
The PCI address/data signals, AD[31:0], are driven to a stable condition during every
address/data phase. Even when the byte enables indicate that byte lanes carry meaningless
data, the signals carry stable values. Parity is calculated on all bytes regardless of the byte
enables. See Section 7.6.1, “PCI Parity,” for more information.
7.4 PCI Bus Transactions
This section provides descriptions of the PCI bus transactions. All bus transactions follow
the protocol as described in Section 7.3, “PCI Bus Protocol.” Read and write transactions
are similar for the memory and I/O spaces, so they are described as generic read
transactions and generic write transactions.
The timing diagrams in this section show the relationship of significant signals involved in
bus transactions. When a signal is drawn as a solid line, it is actively being driven by the
current master or target. When a signal is drawn as a dashed line, no agent is actively driving
it. High-impedance signals are indicated to have indeterminate values when the dashed line
is between the two rails.
The terms ‘edge’ and ‘clock edge’ always refer to the rising edge of the clock. The terms
‘asserted’ and ‘negated’ always refer to the globally visible state of the signal on the clock
edge, and not to signal transitions. ‘
’ represents a turnaround cycle in the timing
diagrams.
7.4.1 PCI Read Transactions
This section describes PCI single-beat read transactions and PCI burst read transactions.
A read transaction starts with the address phase, occurring when an initiator asserts
FRAME. During the address phase, AD[31:0] contain a valid address and C/BE[3:0]
contain a valid bus command.
The first data phase of a read transaction requires a turnaround cycle. This allows the
transition from the initiator driving AD[31:0] as address signals to the target driving