Motorola MPC8240, Руководство пользователя

Страница: 323 / 642

Chapter 7. PCI Bus Interface 7-11
PCI Bus Protocol
7.3.3 Addressing
PCI defines three physical address spaces—PCI memory space, PCI I/O space, and PCI
configuration space. Access to the PCI memory and I/O space is straightforward, although
one must take into account the MPC8240 address map (map A or map B) being used. The
address maps are described in Chapter 3, “Address Maps.” Access to the PCI configuration
space is described in Section 7.4.5, “Configuration Cycles.”
Address decoding on the PCI bus is performed by every device for every PCI transaction.
Each agent is responsible for decoding its own address. PCI supports two types of address
decoding—positive decoding and subtractive decoding. For positive decoding, each device
is looking for accesses in the address range that the device has been assigned. For
subtractive decoding, one device on the bus is looking for accesses that no other device has
claimed. See Section
7.3.4, “Device Selection,” for information about claiming
transactions.
The information contained in the two low-order address bits (AD[1:0]) varies by the
address space (memory, I/O, or configuration). Regardless of the encoding scheme, the two
low-order address bits are always included in parity calculations.
1100 Memory-read-
multiple Yes (for DMA
cycles)
Yes The memory-read-multiple command functions similarly
to the memory-read command, but it also causes a
prefetch of the next cache line (32 bytes).
Note that for PCI reads from local memory, prefetching
for all reads may be forced by setting bit 2 (PCI
speculative read enable) of PICR1. See
Section 12.1.3.1.2, “Speculative PCI Reads from Local
Memory,” for more information.
1101 Dual-address-
cycle No No The dual-address-cycle command is used to transfer a
64-bit address (in two 32-bit address cycles) to 64-bit
addressable devices. The MPC8240 does not respond to
this command.
1110 Memory-read-
line Yes Yes The memory-read-line command indicates that an
initiator is requesting the transfer of an entire cache line
(32 bytes). This only occurs when the processor is
performing a burst read. Note that PowerPC processors
only perform burst reads when the appropriate cache is
enabled and the transaction is not cache-inhibited.
1111 Memory-write-
and-invalidate Yes (for DMA
cycles)
Yes The memory-write-and-invalidate command indicates
that an initiator is transferring an entire cache line
(32 bytes); if this data is in any cacheable memory, that
cache line needs to be invalidated.
1
Reserved command encodings are reserved for future use. The MPC8240 does not respond to these commands.
Table 7-2. PCI Bus Commands (Continued)
C/BE[3:0]
PCI Bus
Command
MPC8240
Supports as
an Initiator
MPC8240
Supports
as a Target
Definition