Motorola MPC8240, Руководство пользователя

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6-10 MPC8240 Integrated Processor User’s Manual
SDRAM Interface Operation
6.2.2 SDRAM Address Multiplexing
This section describes how the MPC8240 translates processor addresses into SDRAM
memory addresses.
The MPC8240 SDRAM memory address signals SDMA[12:0] are labeled with SDMA12
as the most-significant bit (msb) and SDMA0 as the least-significant bit (lsb). Most
SDRAM devices are labeled with A0 as the least significant address input. Therefore, the
MPC8240 SDMA[12:0] signals should be connected to SDRAM devices according to
Table 6-2.
Table 6-6 shows the multiplexing of the internal physical addresses A[0
msb
:31
lsb
] through
SDBA[1:0] and SDMA[12:0] during the row and column phases when operating in 32-bit
mode.
Table 6-5. Supported SDRAM Device Configurations
SDRAM
Device
Density
Device
Organization
Addressing—Row
Bits x Column
Bits x Logical
Banks
1
1
A logical bank is defined for the MPC8240 as a portion of memory addressed through an SDRAM bank select.
MCCR1
[Bank n row]
setting
Number of
Devices in a
Physical Bank
2 , 3
2
A physical bank is defined for the MPC8240 as a portion of memory addressed through an SDRAM chip select.
Certain modules of SDRAM may have two physical banks and require two chip selects to be programmed to
support a single module.
3
Number of devices and size for physical banks are based on a 64-bit data bus, for a 32-bit data bus these
values would be halved.
Physical
Bank Size
3,4
(Mbytes)
4
The physical bank size is the amount of memory addressed by a single SDRAM chip select.
16 Mbit
(2 banks)
4M x 4 bits 13 x 8 x 2
5
5
Not supported for 32-bit data bus
0b01 16 32
11 x 10 x 2 0b11
2M x 8 (or 9) bits 11 x 9 x 2 0b11 8 16
1M x 16 (or 18) bits 11 x 8 x 2
5
0b11 4 8
64 Mbit
(2 banks)
16M x 4 bits 13 x 10 x 2 0b01 16 128
8M x 8 (or 9) bits 13 x 9 x 2 0b01 8 64
4M x 16 (or 18) bits 13 x 8 x 2
5
0b01 4 32
64 Mbit
(4 banks)
16M x 4 bits 12 x 10 x 4 0b00 16 128
8M x 8 (or 9) bits 12 x 9 x 4 0b00 8 64
4M x 16 (or 18) bits 12 x 8 x 4
5
0b00 4 32
2M x 32 (or 36) bits 11 x 8 x 4
5
0b00 2 16
128 Mbit
(2 Banks)
16M x 8 (or 9) bits 13 x 10 x 2 0b01 8 128
8M x 16 (or 18) bits 13 x 9 x 2 0b01 4 64
4M x 32 (or 36) bits 13 x 8 x 2
5
0b01 2 32
128 Mbit
(4 Banks)
16M x 8 (or 9) bits 12 x 10 x 4 0b00 8 128
8M x 16 (or 18) bits 12 x 9 x 4 0b00 4 64
4M x 32 (or 36) bits 12 x 8 x 4
5
0b00 2 32
256 Mbit
(4 banks)
16M x 16 (or 18) bits 12 x 10 x 4 0b00 4 128