Motorola MPC8240, Руководство пользователя

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Chapter 5. PowerPC Processor Core 5-31
Memory Management
memory; demand-paged implies that individual pages are loaded into physical memory
from system memory only when they are first accessed by an executing program.
The PowerPC architecture supports the following three translation methods:
• Address translations disabled. Translation is enabled by setting bits in the
MSR—MSR[IR] enables instruction address translations and MSR[DR] enables
data address translations. Clearing these bits disables translation and the effective
address is used as the physical address.
• Block address translation. The PowerPC architecture defines independent four-entry
BAT arrays for instructions and data that maintain address translations for blocks of
memory. Block sizes range from 128 Kbyte to 256 Mbyte and are software
selectable. The BAT arrays are maintained by system software. The BAT registers,
defined by the PowerPC architecture for block address translations, are shown in
Figure 5-2.
• Demand page mode. The page table contains a number of page table entry groups
(PTEGs). A PTEG contains eight page table entries (PTEs) of eight bytes each;
therefore, each PTEG is 64 bytes long. PTEG addresses are entry points for table
search operations.
The hashed page table is a variable-sized data structure that defines the mapping
between virtual page numbers and physical page numbers. The page table size is a
power of 2; its starting address is a multiple of its size.
On-chip instruction and data TLBs provide address translation in parallel with the
on-chip cache access, incurring no additional time penalty in the event of a TLB hit.
A TLB is a cache of the most recently used page table entries. Software is
responsible for maintaining the consistency of the TLB with memory. In the
MPC8240, the processor core’s TLBs are 64-entry, two-way set-associative caches
that contain instruction and data address translations. The MPC8240’s core provides
hardware assist for software table search operations through the hashed page table
on TLB misses. Supervisor software can invalidate TLB entries selectively.
The MMU also directs the address translation and enforces the protection hierarchy
programmed by the operating system in relation to the supervisor/user privilege level of the
access and in relation to whether the access is a load or store.
5.6.2 MPC8240 Implementation-Specific MMU Features
The instruction and data MMUs in the processor core provide 4 Gbytes of logical address
space accessible to supervisor and user programs with a 4-Kbyte page size and 256-Mbyte
segment size.
The MPC8240 MMUs support up to 4 Petabytes (2
52
) of virtual memory and 4 Gbytes (2
32
)
of physical memory (referred to as real memory in the PowerPC architecture specification)
for instructions and data. Referenced and changed status is maintained by the processor for
each page to assist implementation of a demand-paged virtual memory system.