Motorola MPC8240, Руководство пользователя

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2-34 MPC8240 Integrated Processor User’s Manual
Clocking
2.2.7.8 Debug Clock (CKO)—Output
The debug clock (CKO) signal is an output on the MPC8240. The internal signal reflected
on CKO is determined by either the HID0[ECLK,SBCLK] bits (if PMCR1[CKO_SEL] =
0), or the two-bit PMCR1[CKO_MODE] field (if PMCR1[CKO_SEL] = 1).Both of these
options allow the CKO output driver to be disabled. See Section 5.3.1.2.1, “Hardware
Implementation-Dependent Register 0 (HID0),” and Section 4.3.1, “Power Management
Configuration Register 1 (PMCR1)—Offset 0x70,” for more information.
Note that as described in Section 5.3.1.2.1, “Hardware Implementation-Dependent
Register 0 (HID0)”, the processor core clock is driven on CKO while HRST_CPU and
HRST_CTRL are asserted.
The signal on this output is derived from a variety of internal signals after passing through
differing numbers of internal buffers. This signal is intended for use during system debug;
it is not intended as a reference clock signal.
2.3 Clocking
The following sections describe the clocking on the MPC8240.
2.3.1 Clocking Method
The MPC8240 allows for multiple clock options to suit the needs of various system
configurations. Internally, the MPC8240 uses a phase-locked loop (PLL) circuit to generate
master clocks to the system logic and a second PLL to generate the processor clock. The
system logic PLL is synchronized to the PCI_SYNC_IN input signal.
Figure 2-2 shows a block diagram of the clocking signals in the MPC8240.
Figure 2-2. Clock Subsystem Block Diagram
DLL
PLL
PLL
Processor Core
Core Clk
Peripheral Logic
sys_logic_clk
MPC8240
PCI_CLK[0:4]
PCI_SYNC_OUT
PCI_SYNC_IN
SDRAM_CLK[0:3]
SDRAM_SYNC_OUT
SDRAM_SYNC_IN
OSC_IN