
Block Diagram
http://www.motorola.com/computer/literature
3-15
3
Raven Watchdog Timers
The Raven ASIC contains two Watchdog timers, WDT1, and WDT2. Each
timer is functionally equivalent but independent. These timers will
continuously decrement until they reach a count of 0 or are reloaded by
software. The timeout period is programmable from 1 microsecond up to
4 seconds. If the timer count reaches 0, a timer output signal will be
asserted. The output of Watchdog Timer 1 is routed to generate an MPIC
interrupt. The output of Watchdog Timer 2 is logically ORed onboard to
provide a hard reset.
Following a device reset, WDT1 is enabled with a default timeout of 512
milliseconds and WDT 2 is enabled with a default timeout of 576
milliseconds. Each of these signals is typically delayed an additional 4.8
seconds (2 seconds minimum) using logic external to Raven. Each timer
must be disabled or reloaded by software to prevent a timeout. Software
may reload a new timer value or force the timer to reload a previously
loaded value. To disable or load/reload a timer requires a two step process.
The first step is to write the pattern $55 to the timer register key field which
will arm the timer register to enable an update. The second step is to write
the pattern $AA to the key field along with the new timer information.
During the power-up configuration of the Raven ASIC, PPCBug disables
the two Watchdog timers.
M48T559 Watchdog Timer
The M48T559 contains one Watchdog timer. This Watchdog timer output
is logically ORed with the Raven Watchdog timer 2 output to provide a
hard reset. Refer to the device data sheet and the MCP750 Single Board
Computer Programmer’s Reference Guide for programming information.
Interval Timers
The PBC has three built-in counters that are equivalent to those found in
an 82C54 programmable interval timer. The counters are grouped into one
timer unit, Timer 1, in the PBC. Each counter output has a specific
function: