ACC-JTAG-BR Hardware Reference Guide
Rev 1.0
16
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3.3.2
FPGA Input Signal
There are two methods available if an external input to the FPGA is required.
1. The user can connect directly to connector J7 on the 250S+ using a suitable flexi-rigid cable such
as Molex part number 15266-0267
2. Attach a modified JTAG Breakout Board where the LED on the GPIO signal to be used has been
depopulated and the signal accessed via the header P5
The maximum voltage allowed on each GPIO signal is 3.3V
3.3.3
FPGA-driven UART
The USB connector on the JTAG Breakout Board can be used to connect to an FPGA-driven UART if
the FPGA design in the 250S+ supports it. The UART signals associated with the JTAG Breakout Board
connect to the FPGA as shown in Table 6.
FPGA Pin
XDC Signal Name
I/O Standard
Direction
L13
bkout_txd
LVCMOS18
In
L12
bkout_rxd
LVCMOS18
Out
K13
bkout_rts
LVCMOS18
In
K12
bkout_cts
LVCMOS18
Out
Table 7: JTAG Breakout Board Test signals FPGA Pinout
The maximum voltage allowed on each of these I/O signals is 1.8V
