6
- 9
6.4 Unit Tests
6.4.2 Self-loopback test
6
PRE-OPERATIONAL PROCEDURES AND SETTINGS
(2) Self-loopback test details
The QJ71MB91 performs the following test repeatedly. (Test for one cycle is
performed in approximately one second.)
(a) Programmable controller CPU communication check (The CH1 NEU.LED
flickers.)
Checks that communication with the programmable controller CPU is enabled.
(b) Each interface communication function check (The SD/RD LED of the tested
interface flickers.)
Performs data send and receive while changing data.
*1
* 1 If the data bit length is set to 7 bits, the 8th bit will be ignored during sending and receiving in the
test.
(3) Self-loopback test results check
This test is performed repeatedly. If the ERR.LED is OFF, the test is being operated
normally.
If the ERR.LED turns ON, the test is completed with an error.
When the test is completed abnormally, monitor the self-loopback test results (0FFF
H
)
of the buffer memory and check the error details.
Figure 6.8 Self-loopback test results storage details
Table6.4 Error cause and corrective action
Buffer memory
Cause for corresponding bit ON
Corrective action
Address
Bit position
0FFF
H
(4095)
b0
An error has occurred at programmable controller
CPU.
Remove the error cause in the programmable
controller CPU.
The power capacity is not sufficient.
Review the power capacity.
The module is not mounted correctly.
Mount the module correctly.
An error has occurred at the base unit, extension
cable, programmable controller CPU and
QJ71MB91.
Check each module and remove the error cause.
• Connect the cable correctly.
• Mount the module correctly.
b2
CH2 communication error
Connect the cable correctly.
Review the self-loopback test cable wiring
connections.
b3
CH1 communication error
0/1 0/1
0/1
0
0
b0
b1
b2
b3
b4
to
b15
Self-loopback test results
(0FFF
H
)
1: Programmable controller CPU
Communication error
1: CH2 side
Communication error
1: CH1 side
Communication error
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