APPENDICES
Appendix 2 Special Register List
App
- 68
9
P
a
ra
met
e
rs
10
Device
Exp
la
n
at
ion
11
CP
U
M
odu
le
P
ro
cessi
ng
Ti
m
e
12
P
roc
e
d
ure
f
or W
rit
in
g
P
rog
ra
m t
o CP
U Mo
du
le
A
p
pe
nd
ic
e
s
In
de
x
*9: Function version is B or later.
*13: The module whose first 5 digits of serial No. is "09012" or later.
Number
Name
Meaning
Explanation
Set by
(When Set)
Corres-
ponding
ACPU
D9
Corresponding
CPU
SD778
Refresh
processing
selection when
the COM
instruction is
executed
b0 to b14:
0: Do not
refresh
1: Refresh
b15 bit
0: communication
with peripheral
device is
executed
1: communication
with peripheral
device is
nonexecuted
• Selects whether or not the data is refreshed when the COM instruction is
executed.
• Designation of SD778 is made valid when SM775 turns ON.
U
New
QnU
SD780
Remaining No.
of simultaneous
execution of
CC-Link
dedicated
instruction
0 to 32
• Stores the remaining number of simultaneous execution of the CC-Link
dedicated instructions.
U
New
QnA
SD781
to
SD793
Mask pattern of
IMASK
instruction
Mask pattern
• Stores the mask patterns masked by the IMASK instruction as follows:
S (During
execution)
New
Qn(H)
QnPH
QnPRH
QnU
SD781
to
SD785
Mask pattern of
IMASK
instruction
Mask pattern
• Stores the mask patterns masked by the IMASK instruction as follows:
S (During
execution)
New
Q00J/Q00/Q01
SD794
to
SD795
PID limit setting
(for incomplete
derivative)
0: With limit
1: Without limit
• Specify the limit of each PID loop as shown below.
U
New
Qn(H)
*13
QnPRH
QnU
SD794
PID limit setting
(for incomplete
derivative)
0: With limit
1: Without limit
• Specify the limit of each PID loop as shown below.
U
New
Q00J/Q00/Q01
*9
b0
b1
b2
b3
b4
b5
b6
b14
b15
0
to
I/O refresh
CC-Link refresh
CC-Link IE controller
network or
MELSECNET/H
refresh
0/1
0/1
0/1
0/1 0/1
0/1
0/1
SD778
Automatic refresh of
intelligent function
modules
Execution/non-
execution of
communication with
CPU module
Auto refresh using
QCPU standard area of
multiple CPU system and
reading input/output from
group outside.
Auto refresh using the
multiple CPU high speed
transmission area of
multiple CPU system
SD781
SD782
SD793
l63
l49
l48
l79
l255
l65
l241
l64
l240
b15
b0
b1
to
to
to
to
to
to
SD781
SD782
SD785
l63
l49
l48
l79
l127
l65
l113
l64
l112
b15
b0
b1
to
to
to
SD794
SD795
b15
to
to
b1
b0
Loop16
Loop32
Loop2
Loop18
Loop1
Loop17
SD794
b15
to
to
b1
b0
b7
b8
Loop8
Loop2
Loop1
Содержание Q00CPU
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