APPENDICES
Appendix 2 Special Register List
App
- 42
9
P
a
ra
met
e
rs
10
Device
Exp
la
n
at
ion
11
CP
U
M
odu
le
P
ro
cessi
ng
Ti
m
e
12
P
roc
e
d
ure
f
or W
rit
in
g
P
rog
ra
m t
o CP
U Mo
du
le
A
p
pe
nd
ic
e
s
In
de
x
Number
Name
Meaning
Explanation
Set by
(When Set)
Corres-
ponding
ACPU
D9
Corresponding
CPU
SD62
Annunciator
number
Annunciator
number
• The first annunciator number (F number) to be detected is stored here.
S (Instruction
execution)
D9009
SD63
Number of
annunciators
Number of
annunciators
• Stores the number of annunciators searched.
S (Instruction
execution)
D9124
SD64
Table of
detected
annunciator
numbers
Annunciator
detection number
When F goes ON due to
or
, the F numbers which go
progressively ON from SD64 through SD79 are registered.
The F numbers turned OFF by
are deleted from SD64 - SD79,
and the F numbers stored after the deleted F numbers are shifted to the
preceding registers.
Execution of the
instruction shifts the contents of SD64 to SD79
up by one.
(This can also be done by using the INDICATOR RESET switch on the of
the Q3A/Q4ACPU.)
After 16 annunciators have been detected, detection of the 17th will not be
stored from SD64 through SD79.
S (Instruction
execution)
D9125
SD65
D9126
SD66
D9127
SD67
D9128
SD68
D9129
SD69
D9130
SD70
D9131
SD71
D9132
SD72
New
SD73
New
SD74
New
SD75
New
SD76
New
SD77
New
SD78
New
SD79
New
SD80
CHK number
CHK number
• Error codes detected by the CHK instruction are stored as BCD code.
S (Instruction
execution)
New
QnA
Qn(H)
QnPH
QnPRH
SD90
Step transition
monitoring timer
setting value
(Enabled only
when SFC
program exists)
F number for timer
set value and time
over error
Corresponds to
SM90
• Set the annunciator number (F number) that will
be turned ON when the step transition
monitoring timer setting or monitoring timeout
occurs.
• Turning ON any of SM90 to SM99 during an
active step starts the timer, and if the transition
condition next to the corresponding step is not
met within the timer time limit, the set
annunciator (F) turns ON.
U
D9108
QnA
Qn(H)
QnPH
QnPRH
SD91
Corresponds to
SM91
D9109
SD92
Corresponds to
SM92
D9110
SD93
Corresponds to
SM93
D9111
SD94
Corresponds to
SM94
D9112
SD95
Corresponds to
SM95
D9113
SD96
Corresponds to
SM96
D9114
SD97
Corresponds to
SM97
New
SD98
Corresponds to
SM98
New
SD99
Corresponds to
SM99
New
OUT F
SET F
RST F
LEDR
SD62 0
50 50 50 50 50 50 50 50 50 50 50 99 (Number
detected)
SD63 0
1
2
3
2
3
4
5
6
7
8
9
8
0
50 50 50 50 50 50 50 50 50 50 50 99
SD64
SD65
SD66
SD67
SD68
SD69
SD70
SD71
SD72
SD73
SD74
SD75
SD76
SD77
SD78
SD79
0
0
25 25 99 99 99 99 99 99 99 99 15
0
0
0
99
0
15 15 15 15 15 15 15 70
0
0
0
0
0
0
70 70 70 70 70 70 65
0
0
0
0
0
0
0
65 65 65 65 65 38
0
0
0
0
0
0
0
0
38 38 38 38 110
0
0
0
0
0
0
0
0
0 110 110 110 151
0
0 151
0
0
0
0
0
0
0
0
0
151 210
0
0
0
0
0
0
0
0
0
0
0
210
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(Number of
annunciators
detected)
(Number
detected)
SET
F50
SET
F25
SET
F99
RST
F25
SET
F15
SET
F70
SET
F65
SET
F38
SET
F110
SET
F151
SET
F210 LEDR
b15
b7
b0
b8
F number setting
(0 to 255)
Timer time limit
setting
(1 to 255s:
(1s units))
to
to
Содержание Q00CPU
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