Mitsubishi NZ2GFCF-D62PD2, Руководство пользователя

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APPENDICES
A
Appendix 4 Intern
al C
ontrol Cycle and R
espo
nse D
elay T
ime
Appendix 4
Internal Control Cycle and Response Delay
Time
For the high-speed counter module, responses are delayed by the causes shown in (1) to (3).
(1) Scan time of the program in the master station (SM)
This scan time causes delays of remote I/O signals, remote registers, and remote buffer memory.
(2) Link scan time (LS)
This is the time taken for sending data from each station on the network and finishing the one cycle.
For details, refer to the following.
User's manual for the master/local module used
(3) Control cycle of the high-speed counter module (
Δ
T
2
)
Up to
Δ
T
1
(
Δ
T
2
×2) delay occurs until the high-speed counter module completes processing after the module
reads remote output signals, remote registers, and remote buffer memory updated by the program.
In addition, the update timing of remote input signals, remote registers, and remote buffer memory fluctuates
within one control cycle.
Abbreviation Description Remarks
Δ T
1
Indicates the maximum delay time of internal processing. (
Δ
T
2
× 2).
Link scan time is not included in Δ T
1
.
⎯
Δ T
2
Internal control cycle time (0.5ms)
Link scan time is not included in
Δ T
2
.
⎯
Δ
T
3
Processing time for acquiring data for the maximum setting number of
steps of cam switches (16 points × 16 steps) and analyzing them (40ms) The smaller the number of steps, the
shorter the processing time.