128
When the latch counter function is performed by CH
Latch counter input terminal (LATCH1, LATCH2), the operation
response time follows CH
Latch counter input response time setting (address: 0129
H
.b4 to b5, 0149
H
.b4 to b5). Since
CH
Latch count value (Latch counter input terminal) (RWr18 to RWr19, RWr30 to RWr31) is updated synchronizing with
the internal control cycle, a maximum of delay time shown below occurs until the acquired value is stored.
•
Δ
T
1
*1
+ Setting time of CH
Latch counter input response time setting (address: 0129
H
.b4 to b5, 0149
H
.b4 to b5)
*1
For
Δ
T
1
, refer to Page 283, Appendix 4.
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