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MELSEC-Q
3 SPECIFICATIONS
3.4 Buffer Memory
3.4.1 Buffer memory assignment
The following explanation is mentioned based on Q68DAV and Q68DAI with 8-channel
analog output (CH1 to CH8).
Table 3.6 Buffer memory assignment
Address
Hexadecimal
Decimal
Description
Default
2
Read/write
3
0
H
0
D/A conversion enable/disable
Q62DA : 3
H
Q64DA : F
H
Q68DAV
:
FF
H
Q68DA
I
:
FF
H
R/W
1
H
1
CH1 Digital value
0
R/W
2
H
2
CH2 Digital value
0
R/W
3
H
3
CH3 Digital value
1
0
R/W
4
H
4
CH4 Digital value
1
0
R/W
5
H
5
CH5 Digital value
1
0
R/W
6
H
6
CH6 Digital value
1
0
R/W
7
H
7
CH7 Digital value
1
0
R/W
8
H
8
CH8 Digital value
1
0
R/W
9
H
9
—
—
A
H
10
System area
—
—
B
H
11
CH1 Set value check code
0
R
C
H
12
CH2 Set value check code
0
R
D
H
13
CH3 Set value check code
1
0
R
E
H
14
CH4 Set value check code
1
0
R
F
H
15
CH5 Set value check code
1
0
R
10
H
16
CH6 Set value check code
1
0
R
11
H
17
CH7 Set value check code
1
0
R
12
H
18
CH8 Set value check code
1
0
R
13
H
19
Error code
0
R/W
14
H
20
Setting range (CH1 to CH4)
Q62DA, Q64DA,
Q68DAI: 0
H
Q68DAV: 2222
H
R
15
H
21
Setting range (CH5 to CH8)
Q62DA, Q64DA,
Q68DAI: 0
H
Q68DAV: 2222
H
R
16
H
22
Offset/gain setting mode
Offset specification
0
R/W
17
H
23
Offset/gain setting mode
Gain specification
0
R/W
18
H
24
Offset/gain adjustment value specification
0
R/W
1 For Q62DA, buffer memory address for CH3 to CH8 is the system area.
For Q64DA, buffer memory address for CH5 to CH8 is the system area.
2 This is the initial value set after the power is turned on or the PLC CPU is reset.
3 Indicates whether reading and writing to/from a sequence program are enabled.
R : Reading enabled W : Writing enabled
