3 - 12 3 - 12
MELSEC-Q
3 SPECIFICATIONS
3.2.3 Analog output test during PLC CPU STOP
When the PLC CPU stops, an analog output test as shown in Table 3.4 can be
performed.
The analog output test performs the following operations in GX Developer device
testing or GX Configurator-DA selection testing described in Section 5.6.1.
• Sets the output enable/disable flag (Y1 to Y8) for the channel to be tested to enable
(OFF ON).
• Writes a digital value equivalent to the analog value to be output in CH. digital
value (see Table 3.6 in Section 3.4.1) in the buffer memory.
This function is performed with the D/A conversion module of function version B or
later.
Table 3.4 List of analog output test
D/A conversion
enable/disable
Setting (Un\G0)
Enable
Disable
Setting
combination
CH output
enable/disable
flags (Y1 to Y8)
Enable
Disable
Enable
disable
Analog output test
Allowed
Not allowed
1
1 Perform the analog output test after changing the D/A conversion enable/disable setting
(buffer memory address 0: Un\G0) to enable.