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7521
7521
Plus / N N/B MAINTENANCE
Plus / N N/B MAINTENANCE
5. Pin Descriptions Of Major Components
5.2 SiS630S Slot 1/Socket 370 2D/3D Ultra-AGP™ Single Chipset
PCI Interface
Name
Tolerance Power
Plane
Type
Attr
Description
STOP#
3.3V/5V
MAIN
I/O
Stop# :
STOP# indicates that the bus master must start
terminating its current PCI bus cycle at the next
clock edge and release control of the PCI bus. STOP#
is used for disconnection, retry, and target-abortion
sequences on the PCI bus.
DEVSEL#
3.3V/5V
MAIN
I/O
Device Select :
As a PCI target, SiS Chip asserts
DEVSEL# by doing positive or subtractive decoding.
SiS Chip positively asserts DEVSEL# when the
DRAM address is being accessed by a PCI master, PCI
configuration registers or embedded controllers’
registers are being addressed, or the BIOS memory
space is being accessed. The low 16K I/O space and
low 16M memory space are responded subtractively.
The DEVESEL# is an input pin when SiS Chip is
acting as a PCI master. It is asserted by the addressed
agent to claim the current transaction.
PLOCK#
3.3V/5V
MAIN
I/O
PCI Lock :
When PLOCK# is sampled asserted at the
beginning of a PCI cycle, SiS630 considers itself being
locked and remains in the locked state until PLOCK#
is sampled and negated at the following PCI cycle.
PREQ[2:0]#
3.3V/5V
MAIN
I
PCI Bus Request :
PCI Bus Master Request Signals
PGNT[2:0]#
3.3V
MAIN
O
PCI Bus Grant :
PCI Bus Master Grant Signals
INT[A:D]#
3.3V/5V
MAIN
I
PCI interrupt A,B,C,D :
The PCI interrupts will be
connected to the inputs of the internal Interrupt
controller through the rerouting logic associated with
each PCI interrupt.
PCIRST#
3.3V
AUX
O
PCI Bus Reset :
PCIRST# will be asserted during
the period when PWROK is low, and will be kept on
asserting until about 24ms after PWROK goes high.
SERR#
3.3V/5V
MAIN
I
System Error :
When sampled active low, a non-
maskable interrupt (NMI) can be generated to CPU if
enabled.
Name
Tolerance Power
Plane
Type
Attr
Description
IIOW[A:B]#
3.3V
MAIN
O
Primary/Secondary Channel IOW# Signals
ICHRDY[A:B]
3.3V/5V
MAIN
I
Primary/Secondary Channel ICHRDY# Signals
IDREQ[A:B]
3.3V/5V
MAIN
I
Primary/Secondary Channel DMA Request Signals
IDACK[A:B]#
3.3V
MAIN
O
Primary/Secondary Channel DMACK# Signals
IIRQ[A:B]
3.3V/5V
MAIN
I
Primary/Secondary Channel Interrupt Signals
IDSAA[2:0]
3.3V
MAIN
O
Primary Channel Address [2:0]
IDSAB[2:0]
3.3V
MAIN
O
Secondary Channel Address [2:0]
CBLID[A:B]
3.3V/5V
MAIN
I
Primary/Secondary Ultra-66 Cable ID
VGA Interface
Name
Tolerance Power
Plane
Type
Attr
Description
HSYNC
3.3V
MAIN
O
Horizontal Sync
VSYNC
3.3V
MAIN
O
Vertical Sync
SSYNC
3.3V
MAIN
O
Stereo Sync
DDCCLK
3.3V/5V
MAIN
I/O Display Data Channel Clock Line
DDCDATA
3.3V/5V
MAIN
I/O Display Data Channel Data Line
COMP
MAIN
AI
Compensation Pin:
Connect this pin to AVDD via a
0.1uF capacitor
RSET
MAIN
AI
Reference Resistor:
An external resistor is
connected between the RSET pin and AGND to
control the
magnitude of the full-scale current.
VREF
MAIN
AI
Voltage Reference:
Connect 0.1uF Capacitor to
Ground.
VCS#
3.3V
MAIN
I/O VGA Frame Buffer Cache Chip Select
ROUT
MAIN
AO Red Signal Output
GOUT
MAIN
AO Green Signal Output
BOUT
MAIN
AO Blue Signal Output
VBA1
VBCLK
PLPWDN#
3.3V
MAIN
O
I/O
O
Display Memory Bank Select:
When 128bits
DRAM interface enable, it represents the Memory
Bank Select
Digital Video Clock Input:
When Video Bridge
connected, it represents the Digital Video Clock
Input
Panel Power Down
When external LCD transmitter
connected, it represents power down.
PCI IDE Interface
Name
Tolerance Power
Plane
Type
Attr
Description
IDA[15:0]
3.3V/5V
MAIN
I/O Primary Channel Data Bus
IDB[15:0]
3.3V/5V
MAIN
I/O Secondary Channel Data Bus
IDECSA[1:0]#
3.3V
MAIN
O
Primary Channel CS[1:0]
IDECSB[1:0]#
3.3V
MAIN
O
Secondary Channel CS[1:0]
IIOR[A:B]#
3.3V
MAIN
O
Primary/Secondary Channel IOR# Signals
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