MIPS MIPS32 74K Series, Руководство по программированию

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5.2 MIPS32® Architecture Release 2 - enhanced interrupt system(s)
Programming the MIPS32® 74K™ Core Family, Revision 02.14 70
The original MIPS32 specification adds an option to this. If you set the
Cause[IV]
bit, the same priority-blind inter-
rupt handling happens but control is passed to an interrupt exception entry point which is separate from the general
exception handler.
5.2.2 VI mode - multiple entry points, interrupt signalling and priority
The traditional interrupt system fits with a RISC philosophy (it leaves all interrupt priority policy to software). It’s
also OK with complex operating systems, which commonly have a single piece of code which does the housekeeping
associated with interrupts prior to calling an individual device-interrupt handler.
A single entry point doesn’t fit so well with embedded systems using very low-level interrupt handlers to perform
small near-the-hardware tasks. So Release 2 of the MIPS32 architecture adds “VI interrupt mode” where interrupts
are despatched to one of eight possible entry points. To make this happen:
1. Config3[VInt] must be set, to indicate that your core has the vectored-interrupts feature - but all cores in the 74K
family have it;
2. You write Cause[IV] = 1 to request that interrupts use the special interrupt entry point; and:
3. You set IntCtl[VS] non-zero, setting the spacing between successive interrupt entry points.
Then interrupt exceptions will go to one of eight distinct entry points. The bit-number in
Cause[IP]
corresponding to
the highest-numbered active interrupt becomes the “vector number” in the range 0-7. The vector number is multiplied
by the “spacing” implied by the OS-written field
IntCtl[VS] (see above) to generate an offset. This offset is then added
to the special interrupt entry point (already an offset of 0x200 from the value defined in EBase ) to produce the entry
point to be used.
If multiple interrupts are active and enabled, the entry point will be the one associated with the higher-numbered
interrupt: in VI mode interrupts are no longer all equal, and the hardware now has some role in interrupt “priority”.
5.2.3 External Interrupt Controller (EIC) mode
Embedded systems have lots of interrupts, typically far exceeding the six input signals traditionally available. Most
systems have an external interrupt controller to allow these interrupts to be masked and selected. If your interrupt con-
troller is “EIC compatible” and you use these features, then you get 63 distinct interrupt entry points.
To do this the same six hardware signals used in traditional and VI modes are redefined as a bus with 64 possible val-
ues
16
: 0 means “no interrupt” and 1-63 represent distinct interrupts. That’s “EIC interrupt mode”, and you’re in EIC
mode if you would be in VI mode (see previous section) and additionally the
Config3[VEIC]
bit is set. EIC mode is a
little deceptive: the programming interface hardly seems to change, but the meaning of fields change quite a bit.
Firstly, once the interrupt bits are grouped the interrupt mask bits in Status[IM] can’t just be bitwise enables any more.
Instead this field (strictly, the 6 high order bits of this field, excluding the mask bits for the software interrupts) is
recycled to become a 6-bit
Status[IPL] (“interrupt priority level”) field. Most of the time (when running application
code, or even normal kernel code) Status[IPL] will be zero; the CPU takes an interrupt exception when the interrupt
controller presents a number higher than the current value of Status[IPL] on its “bus” and interrupts are not otherwise
inhibited.
16. The resulting system will be familiar to anyone who’s used a Motorola 68000 family device (or further back, a DEC PDP/11
or any of its successors).