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AN-49-005 (December 23, 2019) M176825 (R95497) File: AN-49-005(J).doc
This document and its contents are the property of Mini-Circuits
SPI timing diagram
SPI interface AC characteristics
Symbol
Parameter
Min Max Units
f
clk
Serial data clock frequency
10
MHz
t
clkH
Serial clock HIGH time
5
ns
t
clkL
Serial clock LOW time
5
ns
t
LESUP
LE setup time after last clock falling
edge
30
ns
t
LEPW
LE minimum pulse width
20
ns
t
SDSUP
Serial data set-up time before clock
rising edge
5
ns
t
SDHLD
Serial data hold time after clock falling
edge
5
ns
2.3.6
Daisy Chain configuration
Some Mini-Circuits’ models include our novel dynamic addressing daisy-chaining interface
which allows multiple attenuators to be connected together into a Master / Slave chain, with
independent control of each attenuator channel through the single USB or Ethernet connection
of the master unit.
Currently models supporting this function are RCDAT-30G-30 and RCDAT-40G-30
-Connect the unit you wish to use as master to USB or Ethernet control (See
sections 2.3.1
&
–Connect CBL-1.5FT-MMD+, CBL-5FT-MMD+ or equivalent cable from serial out port of
master unit to serial in port of first slave unit.
–Connect CBL-1.5FT-MMD+, CBL-5FT-MMD+ or equivalent cable from serial out port of
first slave unit to serial in port of second slave unit.
–If total power consumption from all RCDAT units exceeds power available from supply
connected to master unit connect additional supplies to the USB ports of slave units as
needed (connecting a power supply to the USB port of a slave unit will automatically cut
off power draw via the serial control port).
Note:
Before connecting slave units it is recommended to disable Ethernet control (see
section 3.3.4) of the slave units to reduce power consumption.
The SPI control uses an 8-bit serial in, parallel-out shift register
buffered by a transparent latch with Data, Clock, and Latch
Enable (LE) voltages compatible with LVTTL. The Data and
Clock inputs allow data to be serially entered into the shift
register, a process that is independent of the state of the LE
input. The Value entered should be desired attenuation x 2, so
for example to set attenuation level of 45.5 dB you will enter 91
decimal which is 0101 1011 in Binary.
The LE input controls the latch. When LE is HIGH, the latch is transparent and the contents
of the serial shift register control the switch. When LE is brought LOW, data in the shift
register is latched.
The shift register should be loaded while LE is held LOW to prevent the attenuation state
from changing as data is entered. The LE input should then be toggled HIGH and brought
LOW again, latching the new data. The timing for this operation is defined by the SPI Timing
Diagram and SPI Interface AC Characteristics below
Pin Number
Function
1
+5 V
DC
2
RS232 Transmit
3
RS232 Receive
4
Not Connected
5
GND
6
Factory Use
7
SPI LE
8
SPI Clock
9
SPI Data
