MicroSys Electronics miriac SBC-LS1028A, Руководство пользователя

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System Core, Boot Configuration and On-Board Memory 5
miriac SBC-LS1028A User Manual V 1.0 25/65
© MicroSys Electronics GmbH 2019
5.3
Reset Structure
Pin
Number
on ST6
Signal Name
Signal
Direction
Function
T7 RSTIN# Input to the
module Active low module reset:
while active the module is held in reset state
T5 HRST# Output from
the module Active low peripheral reset:
while active peripheral devices shall be held in
reset state
B4
WDOG-TRIG#
Output from
the module Watchdog service signal from the module which
has to be triggered periodically. When the
watchdog is active and the service stops the
module will be reset.
The watchdog is enabled with the first falling edge
of the WDOG-TRIG# signal.
Once enabled, the watchdog will only be disabled
when a board reset or power cycle occurs.
B77 BSCAN-EN# Input to the
module Active low boundary scan enable signal.
B78
JTRST#
Input to the
module Active low JTAG reset signal:
Depending on “BSCAN-EN” this reset will be
treated differently on the CPU module
B3
PCIE-RST#
Output from
the module Active low PERST# reset:
Auxiliary reset signal to reset connected PCIe
devices
Table 5-1 Reset signal overview
Figure 5-1 Reset Structure (carrier CRX07)