System Core, Boot Configuration and On-Board Memory 5
miriac SBC-LS1028A User Manual
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© MicroSys Electronics GmbH 2019
5
System Core, Boot Configuration
and On-Board Memory
5.1
Processor NXP LS1028A
The QorIQ Layerscape LS1028A processor from NXP contains dual Arm Cortex-
A72 cores. It exposes a wide variety of external interfaces, which are explained in
detail in the following chapters.
The two cores run at a maximum clock speed of 1500 MHz. The CPU frequency
can be clocked down if necessary. Both cores share a single 1MB L2 cache.
5.2
JTAG Chain
The SBC-LS1028A has two separate JTAG chains divided into devices on the
carrier board and devices on the CPU module.
Carrier
The JTAG chain on the carrier (connector ST19) connects to the QSGMII PHY
only.
The pinout allows direct connection of the Goepel TAP header, for example.
CPU Module
The JTAG chain on the module includes the LS1028A processor only. Its JTAG
port is accessible on the carrier at connector ST4.
The JTAG connector footprint provides JTAG signals on a MIPI-10 connector.
Both JTAG and Boundary Scan connections can be established.
SW2 switches between these two modes (see chapter 7.2).
Please see chapter 6.10 for a description of the JTAG connector.